ISD5008PY Nuvoton Technology Corporation of America, ISD5008PY Datasheet - Page 28

• Manufacturer Part Number: ISD5008PY
• Description: IC VOICE REC/PLAY 4-8MIN 28-DIP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISD5008r

Specifications of ISD5008PY

• Interface: SPI/Microwire
• Filter Pass Band: 1.7 ~ 3.4kHz
• Duration: 4 ~ 8 Min
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.600", 15.24mm)
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ISD5008 Product
5.3
The Memo Record mode sets the chip up to
record from the local microphone into the chip’s
Multilevel Storage Array. A connected cellular
telephone or cordless phone chip set may remain
powered down and is not active in this mode. The
path to be used is microphone input to AGC am-
plifier, then through the INPUT SOURCE MUX to the
SUM1 SUMMING amplifier. From there the path
goes through the FILTER MUX, the LOW PASS FILTER,
the SUM2 SUMMING amplifier, then to the MULTI-
LEVEL STORAGE ARRAY. In this instance, we will se-
lect the 5.3 kHz sample rate. The rest of the chip
may be powered down.
24
1. Power up the AGC amplifier—Bit AGPD
2. Select the AGC amplifier through the INPUT
3. Select the INPUT SOURCE MUX (only) to
4. Select the SUM1 SUMMING amplifier
5. Power up the LOWPASS FILTER—Bit FLPD
6. Select the 5.3 kHz sample rate —Bits FLD0
controls the power up state of the AGC
amplifier. This is bit D0 of CFG1 and must
be set to ZERO to power up this stage.
SOURCE MUX —Bit INS0 controls the state of
the INPUT SOURCE MUX. This is bit D9 of
CFG0 and must be set to a ZERO to select
the AGC amplifier.
the S1 SUMMING amplifier—Bits S1M0
and S1M1 control the state of the SUM1
SUMMING amplifier. These are bits D7 and
D8 respectively of CFG1 and they should
be set to the state where D7 is ZERO and D8
is ONE to select the INPUT SOURCE MUX
(only) path.
path through the FILTER MUX—Bit FLS0
controls the state of the FILTER MUX. This is
bit D4 of CFG1 and it must be set to ZERO
to select the SUM1 SUMMING amplifier
path.
controls the power up state of the LOWPASS
FILTER stage. This is bit D1 of CFG1 and it
must be set to ZERO to power up the LOW
PASS FILTER STAGE.
and FLD1 select the Low Pass filter setting
and sample rate to be used during record
MEMO RECORD
To set up the chip for Memo Record, the configu-
ration registers are set up as follows:
Only those portions necessary for this mode are
powered up.
5.4
This mode sets the chip up for local playback of
messages recorded earlier. The playback path is
from the MULTILEVEL STORAGE ARRAY to the FILTER
MUX, then to the LOW PASS FILTER stage. From
there the audio path goes through the SUM2 SUM-
MING amplifier to the VOLUME MUX, through the
VOLUME CONTROL then to the SPEAKER output
stage. We will assume that we are driving a pizeo
speaker element. This audio was previously re-
corded at 8 kHz. All unnecessary stages will be
powered down.
7. Select the LOW PASS FILTER input (only)
1. Select the MULTILEVEL STORAGE ARRAY
2. Power up the LOWPASS FILTER—Bit FLPD
3. Select the 8.0 kHz sample rate —Bits FLD0
and playback. These are bits D2 and D3 of
CFG1. To enable the 5.3 kHz sample rate,
D2 must be set to ZERO and D3 set to ONE.
to the S2 SUMMING amplifier—Bits S2M0
and S2M1 control the state of the SUM2
SUMMING amplifier. These are bits D5 and
D6 respectively of CFG1 and they should
be set to the state where D5 is ZERO and D6
is ONE to select the LOW PASS FILTER (only)
path.
CFG0=0010 0100 0010 0001 (hex 2421).
CFG1=0000 0001 0100 1000 (hex 0148).
path through the FILTER MUX—Bit FLS0,
the state of the FILTER MUX. This is bit D4 of
CFG1 and must be set to ONE to select the
MULTILEVEL STORAGE ARRAY.
controls the power up state of the LOWPASS
FILTER stage. This is bit D1 of CFG1 and it
must be set to ZERO to power up the LOW
PASS FILTER STAGE.
and FLD1 select the Low Pass filter setting
and sample rate to be used during record
MEMO AND CALL PLAYBACK
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