ISD5216EY Nuvoton Technology Corporation of America, ISD5216EY Datasheet - Page 17

• Manufacturer Part Number: ISD5216EY
• Description: IC VOICE REC/PLAY 8-16MIN 28TSOP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISL5216r

Specifications of ISD5216EY

• Interface: I²C
• Filter Pass Band: 1.8 ~ 3.7kHz
• Duration: 8 ~ 16 Min
• Mounting Type: Surface Mount
• Package / Case: 28-TSOP
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The I
also used for flow control. The ISD5216 will hold the clock line low until it is ready to accept another
command/data. The SCL line must be implemented as a bi-directional line like the SDA line.
For example, the sequence of sending the slave address will be as follows:
Since the I
address is known as a “Slave Address”. A Slave Address consists of 7 bits, followed by a single bit
that indicates the direction of data flow. This single bit is 1 for a Write cycle, which indicates the data is
being sent from the current bus master to the device being addressed. This single bit is a 0 for a Read
cycle, which indicates that the data is being sent from the device being addressed to the current bus
master.
Before any data is transmitted on the I
wishes to transfer data to or from. The Slave Address is always sent out as the 1
Start Condition sequence. An example of a Master transmitting an address to a ISD5216 slave is
shown below. In this case, the Master is writing data to the slave and the R/W bit is “0”, i.e. a Write
cycle. All the bits transferred are from the Master to the Slave, except for the indicated Acknowledge
bits.
A common procedure in the ISD5216 is the reading of the Status Bytes. The Read Status condition in
the ISD5216 is triggered when the Master addresses the chip with its proper Slave Address,
immediately followed by the R/W bit set to a “0” and without the Command Byte being sent. This is an
example of the Master sending to the Slave, immediately followed by the Slave sending data back to
the Master. The “N” not-acknowledge cycle from the Master ends the transfer of data from the Slave.
Start Bit
S
1. Send one byte 10000000 {Slave Address, R/W = 0} 80h.
2. Wait for slave to acknowledge (ACK)
3. Next time the clock is pulled high by the master, wait for SCL to actually go high.
2
C Interface in the ISD5216 differs from the standard implementation in the way the SCL line is
SLAVE ADDRESS
7.3.5. Additional ISD5216 flow control
7.3.6. I
2
C protocol allows multiple devices on the bus, each device must have an address. This
2
C Protocol Addressing
acknowledgement
R/W
from slave
W A
Master Transmits to Slave Receiver (Write) Mode
COMMAND BYTE
acknowledgement
2
C interface, the current bus master must address the slave it
from slave
A
High ADDR. BYTE
- 17 -
acknowledgement
from slave
A
Publication Release Date: July 17, 2007
Low ADDR. BYTE
acknowledgement
from slave
st
A
Stop Bit
byte following the
P
ISD5216
Revision B.5