ISD5216EY Nuvoton Technology Corporation of America, ISD5216EY Datasheet - Page 21

• Manufacturer Part Number: ISD5216EY
• Description: IC VOICE REC/PLAY 8-16MIN 28TSOP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISL5216r

Specifications of ISD5216EY

• Interface: I²C
• Filter Pass Band: 1.8 ~ 3.7kHz
• Duration: 8 ~ 16 Min
• Mounting Type: Surface Mount
• Package / Case: 28-TSOP
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

transmitting data that is synchronized with the leading edge (see the timing specifications at the back
of this data sheet).
Note that the specifications are defined by the transmitter speed. The specification of the receiver has to be able to match the
performance of the transmitter.
The word select line indicates the channel being transmitted:
• WS = 0; channel 1 (left)
• WS = 1; channel 2 (right)
WS may change either on a trailing or leading edge of the serial clock, but it doesn’t need to be
symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The WS line
changes one clock period before the MSB is transmitted. This allows the slave transmitter to derive
synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the
receiver to store the previous word and clear the input for the next word (see figure
Transmitter
In the I
slave will usually derive its internal clock signal from an external clock input. This means, taking into
account the propagation delays between master clock and the data and/or word-select signals, the
total delay is simply the sum of:
• the delay between the external (master) clock and the slave’s internal clock; and
• the delay between the internal clock and the data and/or word-select signals.
For data and word-select inputs, the external to internal clock delay is of no consequence because it
only lengthens the effective set-up time (see figure
major part of the time margin is to accommodate the difference between the propagation delay of the
transmitter, and the time required to set up the receiver.
All timing requirements are specified relative to the clock period or to the minimum allowed clock
period of a device. This means that higher data rates can be used in the future.
Note that the specifications are defined by the transmitter speed. The specification of the receiver has to be able to match the
performance of the transmitter.
2
S format, any device can act as the system master by providing the necessary clock signals. A
7.4.2. Word Select
7.4.3. Timing
on previous page.)
T = clock period
T
T > T
R
= minimum allowed clock period for transmitter
R
SCK
and
WS
SD
Timing for I
T
- 21 -
2
t
LC
Timing for I
S Receiver
t
ar
> 0.35T
> 0.2T
2
S Transmitter
t
HC
Publication Release Date: July 17, 2007
t
ar
> 0.35
> 0
V
V
on previous page.) The
H
L
= 0.8V
= 2.0V
ISD5216
Timing for I
Revision B.5
2
S