ISD5216EY Nuvoton Technology Corporation of America, ISD5216EY Datasheet - Page 46

• Manufacturer Part Number: ISD5216EY
• Description: IC VOICE REC/PLAY 8-16MIN 28TSOP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISL5216r

Specifications of ISD5216EY

• Interface: I²C
• Filter Pass Band: 1.8 ~ 3.7kHz
• Duration: 8 ~ 16 Min
• Mounting Type: Surface Mount
• Package / Case: 28-TSOP
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SDI
SDI
SDI
WS
WS
WS
SCK
SCK
SCK
SDIO
SDIO
SDIO
1. Connect the microphone to the CODEC input - Bits CDI1 and CDI0 control the state of the
2. Power up the ADC —Bit ADPD controls the power up state of ADC. This is bit D0 of CFG2
3. Set the CODEC input gain - The input gain setting will depend on the input level at the
4. Set audio interface - Set the interface mode to PCM-interface by setting bit I
5. Set data format - Set the digital data format through bits LAW1 and LAW0. These are bits D3
6. Set Master Clock Division - Set the Master Clock division ratios as described in
7. Power up the DAC — Bit DAPD controls the power up state of the DAC. This is bit D1 of
8. Send DAC output to speaker - Select the DAC path through the OUTPUT MUX—Bits OPS0
9. Power up the Speaker Amplifier —Bits OPA0 and OPA1 control the state of the Speaker
(I2S0)
(I2S0)
(I2S0)
1
1
1
CODEC INPUT MUX. These are the D6 and D5 bits, respectively, of Configuration Register 0
(CFG0) and they should be set to ONE and ZERO.
and it should be a ZERO to power up the ADC.
MIC+/- pins and can be set by the CODEC INPUT GAIN Bits CIG2, CIG1 and CIG0. These
are the D15, D14 and D13 bits, respectively, of Configuration Register 0 (CFG0).
CFG2, to ZERO. This will also enable full duplex mode.
and D2 of CFG2, respectively.
Clock Division Ratio
CFG2 and should be a ZERO to power up the DAC.
and OPS1 control the state of the OUTPUT MUX. These are bits D3 and D4, respectively, of
CFG0 and they should be set to the state where D3 is ONE and D4 is ZERO to select the
DAC path.
and AUX amplifiers. These are bits D1 and D2, respectively, of CFG0. They should be set to
the state where D1 is ONE and D2 is ZERO. This powers up the Speaker Amplifier and
configures it for a higher gain setting (for use with a piezo speaker element) and also powers
down the AUX output stage.
Compressor
Compressor
(LAW1,LAW0)
(LAW1,LAW0)
(LAW1,LAW0)
(LAW1,LAW0)
(LAW1,LAW0)
(LAW1,LAW0)
μ/A-Law
μ/A-Law
Expander
Expander
μ/A-Law
μ/A-Law
2
2
2
2
2
2
on page 25.
(ADPD,HSR0,HPF0,MUTE)
(ADPD,HSR0,HPF0,MUTE)
(DAPD,HSR0,MUTE)
(DAPD,HSR0,MUTE)
DAC
DAC
ADC
ADC
ADC
3
3
4
4
- 46 -
(COG2,COG1,COG0)
(COG2,COG1,COG0)
3
3
(CIG2,CIG1,CIG0)
(CIG2,CIG1,CIG0)
Output
Output
GAIN
GAIN
GAIN
GAIN
Input
Input
3
3
FILTO+
FILTO+
VOL+
VOL+
SUM2+
SUM2+
DAO+
DAO+
DAO-
DAO-
SUM2-
SUM2-
VOL-
VOL-
FILTO-
FILTO-
(OPS1,O PS0)
(OPS1,O PS0)
(CDI1,CDI0)
(CDI1,CDI0)
2
2
2
2
(OPA1,O PA0)
(OPA1,O PA0)
ISD5216
2
Spkr.
Spkr.
AMP
AMP
S0, bit D4 of
SUM2+
SUM2+
SUM2+
SUM2+
INP+
INP+
INP+
INP+
INP-
INP-
INP-
INP-
SUM2-
SUM2-
SUM2-
SUM2-
2
2
Set Master
SPEAKER
SPEAKER
MIC+
MIC+
MIC+
MIC+
MIC -
MIC -
MIC -
MIC -
SP+
SP+
SP-
SP-