CS4525-CNZ Cirrus Logic Inc, CS4525-CNZ Datasheet - Page 28

• Manufacturer Part Number: CS4525-CNZ
• Description: IC AMP AUDIO PWR 30W QUAD 48QFN
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r
• Type: Class Dr

Specifications of CS4525-CNZ

• Output Type: 2-Channel (Stereo) or 4-Channel (Quad)
• Package / Case: 48-QFN
• Max Output Power X Channels @ Load: 30W x 1 @ 4 Ohm; 15W x 2 @ 8 Ohm
• Voltage - Supply: 8 V ~ 18 V
• Features: ADC, Depop, I²C, I²S, Mute, PWM, Short-Circuit and Thermal Protection, Volume Control
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 30 W
• Thd Plus Noise: 10 %
• Operating Supply Voltage: 2.5 V to 5 V
• Supply Current: 54 mA
• Maximum Power Dissipation: 180 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Audio - Load Impedance: 4 Ohms, 6 Ohms, 8 Ohms
• Audio Load Resistance: 8 Ohms, 4 Ohms
• Minimum Operating Temperature: 0 C
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.375 V
• Amplifier Class: D
• No. Of Channels: 4
• Supply Voltage Range: 8V To 18V
• Load Impedance: 4ohm
• Operating Temperature Range: 0°C To +70°C
• Amplifier Case Style: QFN
• No. Of Pins: 48
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1586 - REFERENCE BOARD FOR CS4525 PWM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1264

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6.1.2
6.1.2.1
6.1.2.2
Power-Up and Power-Down
The CS4525 will remain in a completely powered-down state with the control port inaccessible until the
RST pin is brought high. Once RST is high, the control port will be accessible, but all other internal blocks
will remain powered-down until they are powered-up via the control port or until hardware mode is en-
tered.
When an external crystal is present on the XTI/XTO pins, software mode will be automatically entered
10 ms after the release of RST. If SYS_CLK is used as an input, software mode is entered by writing to
the control port within 10 ms after the release of RST. If the control port is not written within this time, the
device will begin to operate in hardware mode.
1. Hold RST low until the power supplies and the input SYS_CLK (if used) are stable.
2. Bring RST high.
3. If SYS_CLK is used as an input, initiate a control port write to set the PDnAll bit in register 5Fh within
4. If the LVD pin is tied low and VD, VD_REG, and VA_REG are connected to 2.5 V, clear the SelectVD
5. If VP is connected to a supply voltage less than or equal to 14 V nominal, clear the SelectVP bit in the
6. The desired register settings can be loaded while keeping the PDnAll bit set. Typical initialization set-
7. Clear the PDnAll bit to initiate the power-up sequence.
1. Set the MuteChA, MuteChB, and MuteSub bits in the Mute Control register to mute the audio output.
2. Set the PDnAll bit to power-down the device.
3. Bring RST low to bring the device’s power consumption to an absolute minimum.
4. Remove power.
Referenced Control
PDnAll .................................
SelectVD .............................
SelectVP .............................
MuteChX .............................
MuteSub..............................
Input Configuration..............
Output Configuration ...........
Master Volume ....................
Clock Frequency .................
The device will remain in a low-power state and the control port will be accessible. The device will
automatically enter software mode after 10 ms if an external crystal is present on the XTI/XTO pins,
at which time the output SYS_CLK signal will become active.
10 ms following the release of RST.
This operation causes the device to enter software mode and places it in power-down mode.
bit in the Power Ctrl register to indicate the 2.5 V VD supply level. See
tails.
Foldback Cfg register to indicate the VP supply level.
tings include Input Configuration, Output Configuration, Master Volume, and Clock Frequency.
Recommended Power-Up Sequence
Recommended Power-Down Sequence
Register Location
“Power Down (PDnAll)” on page 89
“Select VD Level (SelectVD)” on page 88
“Select VP Level (SelectVP)” on page 74
“Independent Channel A & B Mute (MuteChX)” on page 84
“Sub Channel Mute (MuteSub)” on page 85
“Input Configuration (Address 02h)” on page 71
“Output Configuration (Address 04h)” on page 73
“Master Volume Control (Address 57h)” on page 82
“Clock Frequency (ClkFreq[1:0])” on page 69
section 6.7 on page 63
CS4525
DS726PP2
for de-