MT29F8G08AAAWP-ET:ATR Micron Technology Inc, MT29F8G08AAAWP-ET:ATR Datasheet
MT29F8G08AAAWP-ET:ATR
Specifications of MT29F8G08AAAWP-ET:ATR
Related parts for MT29F8G08AAAWP-ET:ATR
MT29F8G08AAAWP-ET:ATR Summary of contents
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... PRE pin: prefetch on power up • WP# pin: hardware write protect PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__1.fm - Rev. I 1/06 EN Products and specifications discussed herein are subject to change by Micron without notice 8Gb: x8/x16 Multiplexed NAND Flash Memory Figure 1: 48-Pin TSOP Type 1 Options • Density: ...
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... If the device required is not on this list, contact the factory. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__1.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory ® NAND Flash devices are available in several different configurations and I/O to verify that the part number is offered and valid. ...
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... Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 V Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 CC Timing Diagrams .42 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29bTOC.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 Table of Contents ©2004 Micron Technology, Inc. All rights reserved. ...
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... List of Figures Figure 1: 48-Pin TSOP Type Figure 2: Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Figure 3: NAND Flash Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 4: Pin Assignment (Top View) 48-Pin TSOP Type Figure 5: Memory Map .11 Figure 6: Memory Map x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Figure 7: Array Organization for MT29F2G08AxB (x8 .12 Figure 8: Array Organization for MT29F2G16AxB (x16 .13 Figure 9: Array Organization for MT29F4G08BxB and MT29F8G08FxB (x8) ...
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... BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Figure 54: RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Figure 55: 48-Pin TSOP Type .56 PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29bLOF.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 List of Figures ©2004 Micron Technology, Inc. All rights reserved. ...
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... Table 18: AC Characteristics: Normal Operation .41 Table 19: PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29bLOT.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 6 List of Tables ©2004 Micron Technology, Inc. All rights reserved. ...
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... Micron NAND Flash devices include standard NAND features as well as new features designed to enhance system-level performance. Micron NAND Flash devices use a highly multiplexed 8- or 16-bit bus (I/O[7:0] or I/O[15:0]) to transfer data, addresses, and instructions. The five command pins (CLE, ALE, CE#, RE#, WE#) implement the NAND command bus interface protocol ...
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... NC 24 Notes: 1. CE2# and R/B2# on 8Gb device only. These pins are NC for other configurations. 2. The PRE function is not supported on extended-temperature devices. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Address Register I/O Status Register Command Register 8 ...
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... Notes: 1. The PRE function is not supported on extended-temperature devices. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Description Address latch enable: During the time ALE is HIGH, address information is transferred from I/O[7:0] into the on-chip address register upon a LOW-to-HIGH ...
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... Addressing NAND Flash devices do not contain dedicated address pins. Addresses are loaded using a five-cycle sequence as shown in Figures 7 and 8, on pages 12 and 13 respectively. Table 2 on page 12 presents address functions internal to the x8 device; Table 3 on page 13 covers the same functions for the x16 device ...
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... A27 (4Gb: A28) 0 Block Address Note: Block address and page address = actual page address. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory A1 7 A18 page 63-0 Block Address Page Address within a block page 63-0 ...
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... RA27 RA26 Fourth Fifth LOW LOW Note: CAx = column address; RAx = row address. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 2,112 bytes 2,048 64 2,048 64 64 pages = 1 block 1 Block 1 page 1 block 1 device = (2K + 64) bytes x 64 pages ...
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... LOW LOW Notes: 1. CAx = column address; RAx = row address. 2. I/O[15:8] are not used during the addressing sequence and should be driven LOW. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 1,056 words 1,024 32 1,024 32 64 pages = 1 block ...
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... RA18 Fourth RA27 RA26 LOW LOW Fifth Notes: 1. Die address boundary – 2Gb 2Gb – 4Gb. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 2,112 bytes 2,048 64 2,048 64 64 pages = 1 block 1 Block 1 page 1 block 1 device = (2K + 64) bytes x 64 pages ...
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... LOW LOW Notes: 1. Die address boundary – 2Gb 2Gb – 4Gb. 2. I/O[15:8] are not used during the addressing sequence and should be driven LOW. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 1,056 words 1,024 32 1,024 32 1 Block ...
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... The CE# “Don’t Care” operation allows the NAND Flash to reside on the same asynchro- nous memory bus as other Flash or SRAM devices. Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capa- bility is important for designs that require multiple NAND Flash devices on the same bus ...
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... The minimum value for Rp is determined by the output drive capability of the R/B# sig- nal, the output voltage swing, and V PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Typically R is 25µs. When data is available in the data ...
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... R dependent on external capacitance and resistive loading and output transistor impedance primarily dependent on external pull-up resistor and external capacitive loading ≈ 10ns at 3.3V See TC values in Figure 15 on page 19 for approximate Rp value and TC. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory V (MAX) – V (MAX Σ ...
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... I 1.50mA 1.00mA 0.50mA 0.00mA Figure 15: TC vs. Rp 1.20µs 1.00µs 800ns T 600ns 400ns 200ns 0ns PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 0 2000 4000 6000 8000 10000 2kΩ 4kΩ 6kΩ 8kΩ 10kΩ ...
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... Notes: 1. WP# should be biased to CMOS HIGH or LOW for standby. 2. PRE should be tied to V The PRE function is not supported on extended-temperature devices. 3. Mode selection settings for this table Logic level HIGH Logic level LOW PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 1 RE# WP# PRE H X ...
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... AC Waveforms During Power Transitions Vcc WP# WE# R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory CC reaches approximately 2.5V, the internal voltage detec RPRE) while the first page of data is copied into the data register. t RPRE value. Once the READ is complete and R/B# goes ...
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... PROGRAM FOR INTERNAL DATA MOVE. See Tables 4 and 5 for definition of die address boundaries. 3. RANDOM DATA READ command limited to use within a single page. 4. RANDOM DATA INPUT for PROGRAM command limited to use within a single page. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Cycle 1 00h 31h 1 3Fh ...
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... CE# WE# ALE R/B# RE# I/Ox 00h Address (5 Cycles) PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t R 30h Micron Technology, Inc., reserves the right to change products or specifications without notice. 23 Command Definitions t R (transfer from Flash array rate. (See Figure 18 Data Output (Serial Access) Don‘ ...
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... Cycles) PAGE READ CACHE MODE START 31h; PAGE READ CACHE MODE START LAST 3Fh Micron NAND Flash devices have a cache register that can be used to increase READ operation speed when accessing sequential pages in a block. First, a normal PAGE READ (00h-30h) command sequence is issued. (See Figure 20 on page 25 for operation details ...
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Figure 20: PAGE READ CACHE MODE CLE CE# WE# ALE t R R/B# RE# I/Ox 00h Address (5 Cycles) 30h t DCBSYR1 t DCBSYR2 31h Data Output (Serial Access) 31h Data Output (Serial Access) t DCBSYR2 3fh Data Output (Serial ...
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... READ ID Operation CLE CE# WE# ALE RE# I/Ox Notes: 1. See Table 8 on page 27. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory WHR t REA 90h 00h Address, 1 Cycle Manufacturer Micron Technology, Inc., reserves the right to change products or specifications without notice. 26 ...
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... STATUS command, as shown in Figure 21. Each time the RE# pin is toggled, the updated status will be output on I/O[7:0]. In addition, after a READ STATUS command has been issued to the NAND Flash device, the status register provides continually updated output on I/O[7:0] as long as CE# and RE# are held LOW, i.e., RE# does not have to be toggled. ...
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... Status register bit 6 is “1” when the cache is ready to accept new data. R/B# follows bit 6. See Figure 20 on page 25, and Figure 25 on page 30. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t CLEA t CLR t REA Status ...
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... PROGRAM Operations PROGRAM PAGE 80h-10h Micron NAND Flash devices are inherently page-programmed devices. Within a block, the pages must be programmed consecutively from the least significant bit (LSB) page of the block to most significant bit (MSB) pages of the block. Random page address pro- gramming is prohibited. ...
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... Notes: 1. See Note 3, Table 19 on page 41. 2. Check I/O[6:5] for internal Ready/Busy. Check I/O[1:0] for pass fail. RE# can stay LOW or pulse multiple times after a 70h command. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t CBSY Address/ Address/ ...
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... INTERNAL DATA MOVE operation use a robust ECC scheme that can correct two or more bits per sector. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 31 Command Definitions ...
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... Figure 27: INTERNAL DATA MOVE with RANDOM DATA INPUT R/B# Address I/Ox 00h 35h (5 cycles) PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t R Address 85h (5 cycles Address 85h Data 85h (5 cycles) Unlimited number ...
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... BLOCK ERASE Operation CLE CE# WE# ALE R/B# RE# I/Ox 60h Address Input (3 Cycles) PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t BERS erase time. t BERS D0h 33 Command Definitions 70h Status I ERASE successful I ERASE error Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... I/Ox Table 10: Status Register Contents After RESET Operation Condition Status WP# HIGH Ready WP# LOW Ready and write protected PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t RST after the RESET command is written to the RST FF RESET Command Bit 7 ...
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... WE# I/Ox WP# R/B# Figure 32: PROGRAM Enable WE# I/Ox WP# R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t WW 60h D0h t WW 60h D0h t WW 80h 10h Micron Technology, Inc., reserves the right to change products or specifications without notice. 35 Command Definitions ...
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... Figure 33: PROGRAM Disable WE# I/Ox WP# R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t WW 80h 10h Micron Technology, Inc., reserves the right to change products or specifications without notice. 36 Command Definitions ©2004 Micron Technology, Inc. All rights reserved. ...
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... Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the Flash device, certain precautions must be taken, such as: • Always check status after a WRITE, ERASE, or DATA MOVE operation. ...
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... Micron NAND Flash devices are designed to prevent data corruption during power tran- sitions. V functions are disabled. WP# provides additional hardware protection. WP# should be kept at V allowed for the Flash to initialize before executing any commands. (See Figure 17 on page 21.) PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev. I 1/06 EN ...
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... Table 15: Capacitance Description Input capacitance Input/output capacitance (I/O) Notes: 1. These parameters are verified in device characterization and are not 100 percent tested. 2. Test conditions: T PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Conditions Symbol t CYCLE = 30ns, Icc1 CE ...
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... WE# for data input. 2. For PROGRAM PAGE CACHE MODE operations, the x16 AC characteristics apply for both x16 and x8 devices. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory = 3.0V ±10 3.3V ±10%) CC ...
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... Notes: 1. Eight total to the same page CBSY MAX time depends on timing between internal program completion and data in LPROG = time (last page) – data load time (last page). PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory x16 Symbol Min Max CEA – ...
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... I/Ox Note: x16: I/O[15:8] must be set to “0. Figure 35: ADDRESS LATCH Cycle CLE CE# WE# ALE I/Ox Note: x16: I/O [15:8] must be set to “0.” PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t t CLS CLH ALH ALS ...
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... Figure 36: INPUT DATA LATCH CLE CE# ALE WE# I/Ox Notes Figure 37: SERIAL ACCESS Cycle After READ t CEA CE# t REA t RP RE# I/ R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t ALS Final = 2,111 (x8) or 1,055 (x16). t REA t REH ...
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... Figure 38: STATUS READ Cycle CLE CE# WE# RE# I/Ox Figure 39: PAGE READ CLE CE WE# ALE RE# Col I/Ox 00h Add 1 Add 2 R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t CLEA t CLR t t CLH CLS WHR 70h t WB Col ...
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... Address (5 Cycles) Figure 41: RANDOM DATA READ CLE CE# WE# ALE RE# Col Col Row I/Ox 00h Add 1 Add 2 Add 1 R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t CEA t REA t R 30h Row Row D OUT 30h Add 2 Add 3 ...
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Figure 42: PAGE READ CACHE MODE Timing Diagram, Part CLE t t CLS CLH CE WE# ALE RE Col Col Row Row 00h I/Ox Add 1 Add ...
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Figure 43: PAGE READ CACHE MODE Timing Diagram, Part CLE t t CLS CLH CE# WE# t CEA ALE REA D ...
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Figure 44: PAGE READ CACHE MODE Timing without R/B#, Part CLE t CLS t CLH CE WE# ALE RE Col Col Row Row Row I/Ox 00h Add ...
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Figure 45: PAGE READ CACHE MODE Timing without R/B#, Part ...
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... ALE RE# I/Ox 90h Address, 1 Cycle Figure 47: Program Operation with CE# “Don’t Care” CLE CE# WE# ALE I/Ox 80h Address (5 Cycles) PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory WHR REA 00h Byte 0 Byte 1 1 Manufacturer ID Device ...
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... CLE CE WE# ALE RE# Col Col I/Ox 80h Add 1 Add 2 SERIAL DATA INPUT Command R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t ADL Row Row Row Add 1 Add 2 Add Byte Serial Input x8 device 2,111 byte x16 device 1,055 byte Micron Technology, Inc ...
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... WE# ALE RE# Col Col Row Row I/Ox 00h Add 1 Add 2 Add 1 Add 2 R/B# PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory t ADL Row D D Col IN IN 85h Add 3 N N+1 Add 1 RANDOM DATA Column Address Serial Input ...
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... Add 1 Add 2 Add 3 Add 1 Add 2 SERIAL DATA INPUT R/B# Last Page - 1 Note: PROGRAM PAGE CACHE MODE operations must not cross die address boundaries. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory CBSY Col 80h 15h Add ...
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Figure 52: PROGRAM PAGE CACHE MODE Ending on 15h CLE CE WE# ALE RE# Col Col Row Row Row D IN I/Ox 80h Add 1 Add 2 Add 1 Add 2 Add 3 N SERIAL DATA Serial Input ...
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... AUTO BLOCK ERASE SETUP Command Notes: 1. See Table 8 on page 27 for actual values. Figure 54: RESET Operation CLE CE# WE# R/B# I/Ox PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory BERS Row D0h Add 3 ERASE Command Busy RST ...
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... This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory 20.00 ±0.25 18.40 ±0.08 SEE DETAIL A 1.20 MAX ® ...
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... Updated package drawing. Rev 4/05 • Initial Release PDF: 09005aef818a56a7 / Source: 09005aef81590bdd 2gb_nand_m29b__2.fm - Rev 8Gb: x8/x16 Multiplexed NAND Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. 57 Revision History ©2004 Micron Technology, Inc. All rights reserved. ...