HCTL-2016 Agilent Technologies, Inc., HCTL-2016 Datasheet

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HCTL-2016

Manufacturer Part Number
HCTL-2016
Description
Manufacturer
Agilent Technologies, Inc.
Datasheet

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Devices
Quadrature Decoder/Counter
Interface ICs
Technical Data
Features
• Interfaces Encoder to
• 14 MHz Clock Operation
• Full 4X Decode
• High Noise Immunity:
• 12 or 16-Bit Binary Up/
• Latched Outputs
• 8-Bit Tristate Interface
• 8, 12, or 16-Bit Operating
• Quadrature Decoder Output
• Cascade Output Signals, Up/
• Substantially Reduced
Applications
• Interface Quadrature
• Interface Digital Potentiom-
ESD WARNING: Standard CMOS handling precautions should be observed with the HCTL-20XX family
ICs.
Microprocessor
Schmitt Trigger Inputs Digital
Noise Filter
Down Counter
Modes
Signals, Up/Down and Count
Down and Count
System Software
Incremental Encoders to
Microprocessors
eters to Digital Data Input
Buses
Part Number
HCTL-2000
HCTL-2016
HCTL-2020
12-bit counter. 14 MHz clock operation.
All features of the HCTL-2000. 16-bit counter.
All features of the HCTL-2016. Quadrature decoder output
signals. Cascade output signals.
Note: Agilent Technologies
encoders are not recommended
for use in safety critical
applications. Eg. ABS braking
systems, power steering, life
support systems and critical care
medical equipment. Please
contact sales representative if
more clarification is needed.
Description
HCTL-2000
HCTL-2016
HCTL-2020
Description
The HCTL-2000, 2016, 2020 are
CMOS ICs that perform the
quadrature decoder, counter, and
bus interface function. The
HCTL-20XX family is designed to
improve system performance
Package Drawing
A
A
B

Related parts for HCTL-2016

HCTL-2016 Summary of contents

Page 1

... HCTL-2000 12-bit counter. 14 MHz clock operation. HCTL-2016 All features of the HCTL-2000. 16-bit counter. HCTL-2020 All features of the HCTL-2016. Quadrature decoder output signals. Cascade output signals. ESD WARNING: Standard CMOS handling precautions should be observed with the HCTL-20XX family ICs. Note: Agilent Technologies ...

Page 2

... Ambient Temperature and an 8-bit bus interface. The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL-2000 contains a 12-bit counter. The HCTL-2016 and 2020 contain a 16-bit counter. The HCTL-2020 also contains quadrature decoder 15 1.52 0.13 (0.060 ...

Page 3

Table 3. DC Characteristics V Symbol Parameter [2] V Low-Level Input Voltage IL [2] V High-Level Input Voltage IH V Schmitt-Trigger Positive- T+ Going Threshold V Schmitt-Trigger Negative- T- Going Threshold V Schmitt-Trigger Hysteresis H I Input Current IN [2] ...

Page 4

... These LSTTL-compatible tri-state outputs form an 8-bit output port through which the contents of the 12/16-bit position latch may be read sequential bytes. The high byte, containing bits 8-15, is read first (on the HCTL-2000, the most significant 4 bits of this byte are set to 0 internally). The lower byte, bits 0-7, is read second ...

Page 5

Switching Characteristics Table 5. Switching Characteristics Min/Max specifications at V Symbol Description 1 t Clock period CLK 2 t Pulse width, clock high CHH 3 t [1] Delay time, rising edge of clock to valid, updated count CD information on ...

Page 6

... Figure 4. Bus Control Timing. Figure 5. Decoder, Cascade Output Timing (HCTL-2020 only). 6 ...

Page 7

... Operation A block diagram of the HCTL- 20XX family is shown in Figure 6. The operation of each major function is described in the following sections. Figure 6. Simplified Logic Diagram. Digital Noise Filter The digital noise filter section is responsible for rejecting noise on the incoming quadrature signals. The input section uses two techniques to implement improved noise rejection ...

Page 8

... Based on the past binary state of the two signals and the present state, it outputs a count signal and a direction signal to the internal position counter. In the case of the HCTL-2020, the signals also go to external pins 5 and 16 respectively. Figure 9 shows the quadrature states and the valid state transi- tions ...

Page 9

... The HCTL-2000 can be used in 12-bit mode and sampled at least once every 2047 quadrature counts. 3. The HCTL-2016 or 2020 can be used in 16-bit mode and sampled at least once every 32,767 quadrature counts. D. The system count is > 16 bits so the HCTL-2020 can be ...

Page 10

... Figure 10. Two Byte Read Sequence. Figure 11. Simplified Inhibit Logic. output and whether or not the output bus is in the high-Z state. In the case of the HCTL-2000 the data latch is only 12 bits wide and the upper four bits of the high byte are internally set to zero ...

Page 11

... HCTL-2020 will cause the counter to roll over and a cascade pulse will be generated. A read starting on this clock cycle will show FFFFH from the HCTL- 2020. The external latch should read F0H, but if the host latches the count after the cascade signal propagates through, the external latch will read F1H ...

Page 12

... General Interfacing The 12-bit (HCTL-2000) or 16-bit (HCTL-2016/2020) latch and inhibit logic allows access bits of count with an 8-bit bus. When only 8-bits of count are required, a simple 8-bit (1- byte) mode is available by holding SEL high continuously. This disables the inhibit logic. OE provides control of the tri-state bus, and read timing is shown in Figures 2 and 3 ...

Page 13

Actions 1. On the rising edge of the clock, counter data is transferred to the position data latch, provided the inhibit signal is low. 2. When OE goes low, the outputs of the multiplexer are enabled onto the data lines. ...

Page 14

... Interfacing the HCTL-2020 to a Motorola 6802/8 and Cascading the Counter for 24 Bits Figure 14. A Circuit to Interface to the 6802/8. 14 ...

Page 15

... STAA 0102 location 0102 Figure 15. Memory Addresses and Read Example. used to clock the HCTL-2020. Address AO is connected directly to the SEL pin on the HCTL- 2020. This line selects the low or high byte of data from the HCTL- 2020. Cascading is accomplished by connecting the CNT ...

Page 16

... HIGH BYTE With the first negative edge after OE and SEL go high, the first of the two HCTL- 2020 inhibit reset conditions is met and the 6802 reads the low byte in. 7. The data bus returns to the high impedance state, when OE goes high. 8. With the first negative edge ...

Page 17

... MOV R1, A 009 89 03 ORL P1, 03H 00B 93 RETR Figure 18. A Typical Program for Reading HCTL-20XX with an 8748. is the crystal frequency divided must be enabled by executing the ENT0 CLK instruction after each system reset, but prior to the first encoder position change. An 8748 program which interfaces to the circuit in Figure 17 is given in Figure 18 ...

Page 18

... ORL PORT 1, 02H has just been executed. The program sets SEL high and leaves OE low by writing the correct values to port 1. The HCTL- ORL P1, 02H 20XX detects OE is low and SEL is high on the next falling edge of the CLK, and thus the first inhibit reset condition is met ...

Page 19

... China: 10800 650 0017 Hong Kong: (+65) 271 2451 India, Australia, New Zealand: (+65) 271 2394 Japan: (+81 3) 3335-8152(Domestic/Interna- tional), or 0120-61-1280(Domestic Only) Korea: (+65) 271 2194 Malaysia, Singapore: (+65) 271 2054 Taiwan: (+65) 271 2654 Data subject to change. Copyright © 2002 Agilent Technologies, Inc. Obsoletes 5965-5894E March 6, 2002 5988-5895EN ...

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