HDMP-0440 Agilent Technologies, Inc., HDMP-0440 Datasheet
HDMP-0440
Related parts for HDMP-0440
HDMP-0440 Summary of contents
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... Description The HDMP-0440 is a Quad Port Bypass Circuit (PBC), which provides a low-cost, low-power physical-layer solution for Fibre Channel Arbitrated Loop (FC-AL) disk array configurations. By using a PBC such as the HDMP-0440, hard disks may be pulled out or swapped while other disks in the array are available to the system. ...
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... EQU EQU TTL EQU BLL BLL 1 0 Figure 1. Block diagram of HDMP-0440. 2 terminated with an appropriate resistor. The value of the termination resistor should match the PCB trace differential impedance. EQU INPUT All FM_NODE[n] high-speed differential inputs have an ...
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... SERDES EQU EQU TTL EQU TTL BLL BLL BLL Figure 3. Connection diagram for multiple HDMP-0440s. I/O Type Definitions I/O Type Definition I-LVTTL LVTTL Input O-LVTTL LVTTL Output HS_OUT High Speed Output, LVPECL compatible HS_IN High Speed Input C External Circuit Node S Power Supply or Ground ...
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Pin Definitions Pin Name Pin Pin Type TO_NODE[0]+ 24 HS_OUT TO_NODE[0]- 25 TO_NODE[1]+ 07 TO_NODE[1]- 06 TO_NODE[2]+ 44 TO_NODE[2]- 43 TO_NODE[3]+ 38 TO_NODE[3]- 37 TO_NODE[4]+ 31 TO_NODE[4]- 30 FM_NODE[0]+ 10 HS_IN FM_NODE[0]- 09 FM_NODE[1]+ 04 FM_NODE[1]- 03 FM_NODE[2]+ 41 FM_NODE[2]- ...
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Absolute Maximum Ratings except as specified. Operation in excess of any of these conditions may result in permanent damage to this A device. Continuous operation at these minimum or maximum ratings is not recommended. Symbol Parameter ...
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AC Electrical Specifications + 3. 3. Symbol Parameter T Total Loop Latency from FM_NODE[0] to TO_NODE[0] LOOP_LAT T Per Cell Latency from FM_NODE[4] to TO_NODE[0] CELL_LAT t ...
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Simplified I/O Cells O_LVTTL V CC ESD PROTECTION GND Figure 5. O-LVTTL and I-LVTTL simplified circuit schematic. HS_OUT 75 ESD PROTECTION NOTE: 1. FM_NODE[n] INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT. Figure ...
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... TOP VIEW ALL DIMENSIONS ARE IN MILLIMETERS PART NUMBER HDMP-0440 TOLERANCE Figure 7. HDMP-0440 package drawing. 8 Units mW C/W for this device is 57ºC/W. is measured on a standard 3x3” FR4 PCB in a still air ja ja Details Plastic 85% Tin, 15% Lead 200-800 micro-inches 0.33 mm max 0.10 mm max ...
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... TO_NODE [1]– 6 TO_NODE [1]+ 7 GND 8 FM_NODE [0]– 9 FM_NODE [0 GND nnnn-nnn = WAFER LOT – BUILD NUMBER; Rz.zz = DIE REVISION SUPPLIER CODE YYWW = DATE CODE ( YY = YEAR WORK WEEK); COUNTRY = COUNTRY OF MANUFACTURE (ON BACK SIDE) Figure 8. HDMP-0440 package layout and marking, top view. GND GND ...
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... Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright © 2003 Agilent Technologies, Inc. April 3, 2003 5988-8563EN ...