HDMP-0552 Agilent Technologies, Inc., HDMP-0552 Datasheet

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HDMP-0552

Manufacturer Part Number
HDMP-0552
Description
Manufacturer
Agilent Technologies, Inc.
Datasheet

Specifications of HDMP-0552

Case
QFP

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Part Number:
HDMP-0552
Manufacturer:
AGILENT
Quantity:
1 000
Description
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and assembly of
this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).
Agilent HDMP-0552 Quad Port Bypass
Circuit with CDR and Data Valid
Detection
For Fibre Channel Arbitrated Loops
Data Sheet
Features
• Supports 1.0625/2.125 GBd Fibre
• Quad PBC/CDR in one package
• CDR location determined by
• Amplitude valid detection on
• Data valid detection on
• Speed select pin for 1 or 2 GBd
• Single REFCLK for 1 or 2 GBd
• CDR selectable via external pin
• Enable/disable equalizers on all
• Enable/disable selected high-
• High speed LVPECL I/O
• Buffered line logic (BLL) outputs
• 1.1 W typical power at V
• Advanced 0.35 µ BiCMOS
• 64 Pin, 10 mm, low cost plastic
Applications
• RAID, JBOD, BTS cabinets
• 1=> 1-4 serial buffer with or
Channel operation
choice of cable input/output
FM_NODE[0] input
FM_NODE[0] input
– Run length violation detection
– Comma detection
– Configurable for both single-
operation
operation
inputs
speed output drivers
(no external bias resistors
required)
technology
QFP package
without CDR
frame and multi-frame
detection
CC
= 3.3 V

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HDMP-0552 Summary of contents

Page 1

... Description CAUTION: As with all semiconductor ICs advised that normal static precautions be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD). Agilent HDMP-0552 Quad Port Bypass Circuit with CDR and Data Valid Detection For Fibre Channel Arbitrated Loops ...

Page 2

... HDMP-0552 Block Diagram CDR 2 Data Valid Output REFCLK Input and REF_RATE Control Amplitude Valid Output ...

Page 3

... Equalizer Input Figure 1 - Block Diagram of HDMP-0552 3 W BYPASS[n]- Input CDR DV CPLL BLL Output Unused outputs should be turned off independently. This reduces power and reduces the potential for crosstalk effects caused by incorrect terminations ...

Page 4

Hard Disk A Hard Disk B SERDES SERDES Figure 2 - Connection Diagram for CDR at First Cell Hard Disk A SERDES Figure 3 - Connection Diagram for CDR at Last Cell ...

Page 5

... Table 1 - Pin Definitions for HDMP-0552. Refer to Figure 4 for pin layout Pin Name Pin Pin Type MODE_DV 24 I-LVTTL FSEL 25 I-LVTTL FM_NODE[0]_DV 23 O-LVTTL FM_NODE[0]_AV 59 O-LVTTL TO_NODE[0]+ 57 HS_OUT TO_NODE[0]- 56 TO_NODE[1]+ 32 TO_NODE[1]- 31 TO_NODE[2]+ 35 TO_NODE[2]- 34 TO_NODE[3]+ 44 TO_NODE[3]- 43 TO_NODE[4]+ 47 TO_NODE[4]- 46 FM_NODE[0]+ 54 HS_IN FM_NODE[0]- 53 FM_NODE[1]+ 29 FM_NODE[1]- 28 FM_NODE[2]+ 38 FM_NODE[2]- ...

Page 6

... Table 1 (continued) - Pin Definitions for HDMP-0552. Refer to Figure 4 for pin layout Pin Name Pin Pin Type OUT_SEL 60 I-LVTTL ND0 64 I-LVTTL ND1 63 I-LVTTL ND2 62 I-LVTTL ND3 20 I-LVTTL ND4 21 I-LVTTL TDO 2 O-LVTTL TDI 3 I-LVTTL nTRST 4 I-LVTTL TMS 5 I-LVTTL TCK 6 I-LVTTL GND Pin Description Output Select: Allows user to turn on/off any output driver ...

Page 7

... S YYWW Rz.zz REF_RATE 12 VCC 13 REFCLK 14 GND 15 CPLL1 Figure 4 - HDMP-0552 package layout and marking, top view xxxxxxx-nn = wafer lot - build number Supplier Code; YYWW = Date Code (YY = year work week); Rz.zz = Die Revision; COUNTRY (on back side) = country of manufacture. 7 Agilent HDMP-0552 xxxxxxx-nn 48 VCC 47 TO_NODE [ ...

Page 8

... CDR position ( Cell connected to Cable 0 x denotes CDR position with respect to hard disks. For example means the CDR is between disk A and disk B. HDMP-0552 Electrical Specifications Absolute Maximum Ratings ° + except as specified. Operation in excess of any of these conditions may result in permanent damage to this device. ...

Page 9

Guaranteed Operating Rates Ta = 0° +80°C , VCC = 3. 3.45 V Serial Clock Rate FC (MBd) Minimum Maximum 1,040 1,080 2,080 2,160 HS_OUT +TO_NODE -TO_NODE GND ...

Page 10

AC Electrical Specifications Ta = 0° +80°C , VCC = 3. 3.45 V Symbol Parameter tdelay1 Total Loop Latency from FM_NODE[0] to TO_NODE[0] tdelay2 Per Cell Latency from FM_NODE[x] to TO_NODE[x+1] tr,LVTTLin Input LVTTL Rise ...

Page 11

... Figure 9 - Setup for Measurement of Deterministic Jitter 11 Units Maximum bits 2500 µs 500 HDMP-0552 ± FM_NODE[0] BIAS REF CLK 1.4 VARIABLE DELAY TRIGGER 83480A DIGITAL COMMUNICATION ANALYZER HDMP-0552 ± FM_NODE[0] BIAS REF CLK 1.4 VARIABLE DELAY 1/2 TRIGGER 83480A DIGITAL COMMUNICATION ANALYZER BYPASS - [ BYPASS - [1] BYPASS - [2] BYPASS - [3] BYPASS - [4] ± ...

Page 12

... TOP VIEW Dimensional Parameter A A1 (millimeters) Value 2.45 0.25 Tolerance MAX MIN Figure 10 - HDMP-0552 Package Drawing www.semiconductor.agilent.com Data subject to change. Copyright © 2001 Agilent Technologies, Inc. October 15, 2001 5988-3998EN Details Plastic 85% Tin, 15% Lead 300-800 micro-inches 0.08 mm maximum 0.08 mm maximum SEATING PLANE ...

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