ADV7152LS220 Analog Devices, ADV7152LS220 Datasheet
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ADV7152LS220
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ADV7152LS220 Summary of contents
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... CLOCK ECL TO CMOS CLOCK REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...
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ADV7152–SPECIFICATIONS pF); IOR, IOG, IOB = GND. All specifications T L Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity Gray Scale Error Coding DIGITAL INPUTS (Excluding CLOCK, CLOCK) Input High Voltage, V ...
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TIMING CHARACTERISTICS IOR, IOG, I0B = GND. All specifications T MIN CLOCK CONTROL AND PIXEL PORT 220 MHz 170 MHz Parameter Version Version f 220 170 CLOCK t 4. ...
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ADV7152 NOTES 1 TTL input values are volts, with input rise/fall times V –0 –1.8 V, with input rise/fall times AA AA puts. Analog output load 10 pF. Databus (D0–D9) loaded as shown in ...
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CLOCK LOADOUT LOADIN PIXEL INPUT N+1 N+1 DATA* IOR, IOR ANALOG IOG, IOG OUTPUT IOB, IOB DATA I , SYNCOUT PLL t PD *INCLUDES PIXEL DATA (R0–R7, G0–G7, B0–B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; ...
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ADV7152 t 13 SCKIN BLANK SCKOUT *INCLUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK Figure 7. Video Data Shift Clock Input (SCKIN) & BLANK vs. Video Data Shift Clock Output (SCKOUT) CLOCK IOR, IOR IOG, IOG ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog Output Short Circuit to any Power Supply or Common can indefinite duration. ORDERING GUIDE Speed 220 MHz ADV7152LS220 110 MHz ADV7152LS110 170 MHz ADV7152LS170 85 MHz 135 MHz ADV7152LS135 NOTES 1 ADV7152 is packaged in a 100-pin plastic quad flatpack, QFP ...
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ADV7152 Mnemonic RED ( – GREEN ( – BLUE ( ...
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Mnemonic R/W C0, C1 IOR; IOR, IOG; IOG, IOB; IOB V REF R SET COMP I PLL V AA GND REV. B Function Read/Write Control (TTL Compatible Input). This input determines whether data is written to or read from the ...
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ADV7152 applications. The part is controlled and programmed through the microprocessor (MPU) port. The part also contains a num- ber of onboard test registers, associated with self diagnostic test- ing of the device. The individual Red, Green and Blue pixel ...
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Color data is latched into the parts pixel port on every rising edge of LOADIN (see Timing Waveform, Figure 3). The required frequency of LOADIN is determined by the multiplex rate, where 2:1 Multiplex Mode LOADIN ...
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ADV7152 Alternatively, the ADV7152 CLOCK inputs can be driven by a Programmable Clock Generator (Figure 13), such as the ICS1562. The ICS1562 is a monolithic, phase-locked-loop, clock generator chip capable of synthesizing differential ECL output frequencies in a ...
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Pipeline Delay and On-Board Calibration The ADV7152 has a fixed number of pipeline delays (t long as timings t and -t are met. However fixed pipeline 10 11 delay is not a requirement, timings t and -t 10 ...
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ADV7152 This mode allows for the display of 256 simultaneous colors out of a total palette of millions of addressable colors. 15-Bit “Gamma” True Color (CR24, CR25, CR26, CR27 = and ...
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ADV7152 Data is read from the color palette by first writing to the address register of the color palette location to be read. The MPU per- forms three successive read cycles from each of the red, green and blue locations ...
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Databus R (D9–D0 DB7–DB0 DB7–DB0 DB7–DB0 DB9–DB2 DB1–DB0 DB9–DB2 DB1–DB0 DB9–DB2 ...
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ADV7152 REGISTER PROGRAMMING The following section describes each register, including Address Register, Mode Register and each of the nine Control Registers in terms of its configuration. Address Register (A7–A0) As illustrated in the previous tables, the C0 and C1 control ...
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DAC Test Register (Address Reg (A7–A0) = 01H) This register is used when the device is in test/diagnostic mode 30-bit (10 bits each for RED, GREEN and BLUE) wide read-only register which allows MPU access to the ...
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ADV7152 COMMAND REGISTER 2 (CR2) (Address Reg (A7–A0) = 06H) This register contains a number of control bits as shown in the diagram. CR2 is a 10-bit wide register. However for program- ming purposes, it may be considered as an ...
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COMMAND REGISTER 3 (CR3) (Address Reg (A7–A0) = 07H) This register contains a number of control bits as shown in the diagram. CR3 is a 10-bit wide register. However for program- ming purposes, it may be considered as an 8-bit ...
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ADV7152 DIGITAL-TO-ANALOG CONVERTERS (DACS) AND VIDEO OUTPUTS The ADV7152 contains three high speed video DACs. The DAC outputs are represented as the three primary analog color signals IOR (red video), IOG (green video) and IOB (blue video). Other analog signals ...
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Variations on RS-343A Various other video output configurations can be implemented by the ADV7152, including RS-170. Values of R lar output video formats/levels are calculated by using the equa- tions for R given in the “Pin Configuration” section. The SET ...
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ADV7152 BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7152 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high ...
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0.1 F COMP ADV7152 GND CLOCK GENERATOR CLOCK GRAPHICS PROCESSOR/ CONTROLLER FRAME BUFFER/ VIDEO MEMORY REV. B POWER SUPPLY DECOUPLING (0.1 F AND 0.01 F CAPACITOR FOR EACH V 0.1 F 0.01 F 0.01 ...
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ADV7152 10-Bit DACs 10-bit RAM-DAC resolution allows for nonlinear video correc- tion, in particular Gamma Correction. The ADV7152 allows for an increase in color resolution from 24-bit to 30-bit effective color without the necessity of a 30-bit deep frame buffer. ...
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Palette Priority Select Inputs The palette priority selection inputs allow up to four separate palette devices to be used in a single system to drive a single monitor. The IOR, IOG and IOB analog video output signals of each device ...
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ADV7152 ADV7152 Initialization After power has been supplied, the ADV7152 must be initial- ized. The Mode Register and Control Registers must be set. The values written to the various registers will be determined by the desired operating mode of the ...
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Example 2 Color Mode 24-Bit Gamma Corrected True Color (30 Bits) Multiplexing 2:1 Databus 10-Bit RAM-DAC Resolution 10-Bit SYNC Ignored Pedestal 0 IRE Calibration Every Vertical Sync Register Initialization Write 0FH to Mode Register (MR1) Write 0EH to Mode Register ...
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ADV7152 SYNC BLANK GRAPHICS PIPELINE PIXEL INPUT DATA MUX TRIGGER DECODE The ADV7152 contains onboard circuitry which enables both device and system level test diagnostics. The test circuitry can be used to test the frame buffer memory as well as ...
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THERMAL AND ENVIRONMENTAL CONSIDERATIONS The ADV7152 is a very highly integrated monolithic silicon device. This high level of integration, in such a small package, inevitably leads to consideration of thermal and environmental conditions in which the ADV7152 must operate. Reliability ...
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ADV7152 MAX 0.004 (0.102) MAX 0.134 (3.40) MAX APPENDIX 8 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 100-Lead Plastic Power Quad Flatpack (S-100) 0.952 (24.15) 0.932 (23.65) 0.792 (20.10) 0.784 (19.90 TOP ...