RTL8204 REALTEK, RTL8204 Datasheet
RTL8204
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RTL8204 Summary of contents
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... REALTEK SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER 1. Features........................................................................... 2 2. General Description ....................................................... 2 3. Block Diagram................................................................ 3 4. Pin Assignments ............................................................. 4 5. Pin Description ............................................................... 5 5.1 100 Mbps MII & PCS Interface ................................ 5 5.2 SNI (Serial Network Interface): 10Mbps only .......... 5 5.3 Clock Interface .......................................................... 6 5.4 100Mbps Network Interface...................................... 6 5 ...
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... Features The Realtek RTL8201BL is a Fast Ethernet Phyceiver with selectable MII or SNI interface to the MAC chip. It provides the following features: Supports MII/7-wire Interface) interface Supports 10/100Mbps operation Supports half/full duplex operation Support of twisted pair or Fiber mode output IEEE 802.3/802.3u compliant Supports IEEE 802.3u clause 28 auto negotiation ...
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Block Diagram MII Interface 10/100 half/full Switch Logic SNI Interface TXC10 TXD10 RXC10 RXD10 TXC 25M TXD RXC 25M Serial to RXD Parrallel 2002-03-29 100M 5B 4B Data Decoder Alignment 4B 5B Scrambler Encoder 10/100M Auto-negotiation Control Logic 10M ...
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Pin Assignments 37. ANE 38. DUPLEX 39. SPEED 40. RPTR 41. LDPS 42. RESETB 43. ISOLATE 44. M II/SNIB /RTT3 45. DGND 46. X1 47. X2 48. DVDD33 2002-03-29 RTL8201BL 4 RTL8201BL 24. RXER /FXEN 23. CRS 22. RXDV ...
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Pin Description LI: Latched Input in power up or reset I: Input P: Power 5.1 100 Mbps MII & PCS Interface Symbol Type Pin No. TXC O 7 TXEN I 2 TXD[3: RXC O ...
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Clock Interface Symbol Type Pin No 5.4 100Mbps Network Interface Symbol Type Pin No. TPTX TPTX RTSET I 28 TPRX TPRX 5.5 Device Configuration Interface ...
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LED Interface/PHY Address Config These five pins are latched into the RTL8201BL during power up reset to configure PHY address [0:4] used for MII management register interface. And then, in normal operation after initial reset, they are used as ...
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Register Descriptions This section will describe definitions and usage for each of the registers available in the RTL8201BL. 6.1 Register 0 Basic Mode Control Register Address Name Description/Usage 0:<15> Reset This bit sets the status and control registers of ...
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Register 1 Basic Mode Status Register Address Name 1:<15> 100Base- enable 100Base-T4 support 0 = suppress 100Base-T4 support 1:<14> 100Base_TX_ 1 = enable 100Base-TX full duplex support suppress 100Base-TX full duplex support 1:<13> 100BASE_TX_ ...
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Register 4 Auto-negotiation Advertisement Register(ANAR) This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-negotiation. Address Name 4:<15> NP Next Page bit transmitting the primary capability data ...
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This bit will also be set after the link in 100Base is established by parallel detection. 5:<6> 10FD 1 = 10Base-T full ...
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Register 17 Loopback, Bypass, Receiver Error Mask Register(LBREMR) Address Name 17:<15> RPTR Set put the RTL8201BL into repeater mode 17:<14> BP_4B5B Assertion of this bit allows bypassing of the 4B/5B & 5B/4B encoder. 17:<13> BP_SCR Assertion ...
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Register 20 PHY 1_1 Register Address Name 20:<15:0> PHY1_1 PHY 1 register (functions as RTL8139C<78>) 6.13 Register 21 PHY 1_2 Register Address Name 21:<15:0> PHY1_2 PHY 1 register (functions as RTL8139C<78>) 6.14 Register 22 PHY 2 Register Address Name ...
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Functional Description The RTL8201BL Phyceiver is a physical layer device that integrates 10Base-T and 100Base-TX functions and some extra power manage features into a 48 pin single chip which is used in 10/100 Fast Ethernet applications. This device supports ...
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MDC MDIO Preamble ST OP MDC MDIO Preamble ST OP MDIO is sourced by MAC. Clock data into PHY on rising edge of MDC Preamble ...
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UTP mode and MII interface ANE SPEED DUPLEX (Pin 37) (Pin 39) (Pin 38 UTP mode ...
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MII/SNIB: Pull high to set RTL8201BL into MII mode operation, which is the default mode for the RTL8201. This pin pulled low will set the RTL8201BL into SNI mode operation. When set to SNI mode, the RTL8201BL will work ...
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This interface consists of 10Mbps transmit and receive clock generated by PHY, 10Mbps transmit and receive serial data, transmit enable, collision detect, and carry sense signals. 7.7 Power Down, Link Down, Power Saving, and Isolation Modes The RTL8201BL supplies 4 ...
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Transmit Function: The 100Base-FX transmit function is performed as follows: Di-bits of TXD are processed as 100Base-TX, except without scrambler before the NRZI stage. Instead of converting to MLT-3 signals 100Base-TX, the serial data stream is ...
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DVDD33(pin14) 3.3V 0.1uF DVDD33(pin48) 0.1uF 1.2V bandgap voltage 7.12 Far End Fault Indication (FEFI) The MII Reg.1.4 (Remote Fault) is the FEFI bit when 100FX mode is enabled which indicates that FEFI has been detected. FEFI is an alternative in-band ...
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Electrical Characteristics 8.1 D.C. Characteristics 8.1.1. Absolute Maximum Ratings Symbol Conditions Supply Voltage Storage Temp. 8.1.2. Operating Conditions Symbol Conditions Vcc 3.3V 3.3V Supply voltage TA Operating Temperature 8.1.3. Power Dissipation Test condition: VCC=3.3V Symbol P Link down power ...
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A.C. Characteristics 8.2.1 MII Timing of Transmission Cycle Shown is an example transfer of a packet from MAC to PHY in MII interface. Symbol Description t TXCLK high pulse width 1 t TXCLK low pulse width 2 t TXCLK ...
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MII Timing of Reception Cycle Shown is an example of transfer of a packet from PHY to MAC in MII interface Symbol Description t RXCLK high pulse width 1 t RXCLK low pulse width 2 t RXCLK period 3 ...
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SNI Timing of Transmission Cycle Shown is an example transfer of a packet from MAC to PHY in SNI interface. SNI mode only runs in 10Mbps. Symbol Description t TXCLK high pulse width 1 t TXCLK low pulse width ...
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SNI Timing of Reception Cycle Shown is an example of transfer of a packet from PHY to MAC in SNI interface. SNI mode only runs in 10Mbps. Symbol Description t RXCLK high pulse width 1 t RXCLK low pulse ...
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MDC/MDIO timing Symbol Description t MDC high pulse width 1 t MDC low pulse width 2 t MDC period 3 t MDIO setup to MDC rising edge 4 t MDIO hold time from MDC rising edge 5 t MDIO ...
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Crystal and Transformer Specifications 8.3.1 Crystal Specifications Item Parameter 1 Nominal Frequency 2 Oscillation Mode 3 Frequency Tolerance at 25℃ 4 Temperature Characteristics 5 Operating Temperature Range 6 Equivalent Series Resistance 7 Drive Level 8 Load Capacitance 9 Shunt ...
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... PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm 0.50 BSC 0.40 0.60 0.80 APPROVE 1.00 REF 0° 3.5° 9° CHECK 0° 12° TYP 12° TYP REALTEK SEMI-CONDUCTOR CORP. 28 RTL8201BL TITLE: 48LD LQFP ( 7x7x1.4mm) LEADFRAME MATERIAL: DOC. NO. VERSION 1 PAGE OF DWG NO. SS048 - P1 DATE Sept. 25.2000 Rev.1.2 ...
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... Power and Ground pins 6.6 Register 5 Auto-Negotiation Link Partner Ability Register 7.11 3.3V power supply and voltage conversion circuit Schematic Layout Realtek Semiconductor Corp. Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw ...