ALC203 REALTEK, ALC203 Datasheet

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ALC203

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ALC203
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REALTEK
Datasheet

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ALC203
ALC203-LF
TWO-CHANNEL AC’97 2.3 AUDIO CODEC
DATASHEET
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
28 April 2006
Rev. 1.6

Related parts for ALC203

ALC203 Summary of contents

Page 1

... ALC203 ALC203-LF TWO-CHANNEL AC’97 2.3 AUDIO CODEC DATASHEET Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com.tw Rev. 1.6 28 April 2006 ...

Page 2

... Add ordering information. Add lead (Pb)-free and version package identification information on page 4 and on page 48. Update section 6.1.12 MX1A Record Select, page 12. Update section 12. Ordering Information, page 48. Add a note to, and change Susceptibility Voltage data in section 7.1.1 Absolute Maximum Ratings, page 27. ii ALC203 DataSheet Rev1.6 ...

Page 3

... Page -1h, MX66 Sense Function Select ..................................................................................................................... 22 6.3.4 Page -1h, MX68 Sense Function................................................................................................................................ 22 6.3.5 Page -1h, MX6A Sense Detail.................................................................................................................................... 23 6 ...................................................................................................................................................... 24 XTENSION EGISTERS 6.4.1 MX76 GPIO & Interrupt Setup .................................................................................................................................. 24 Two-Channel AC’97 2.3 Audio Codec Table of Contents V I ................................................................................................. 4 ERSION DENTIFICATION -00 ) ........................................................................................................................ 20 AGE H ID-01 ) .......................................................................................................................... 21 H iii ALC203 DataSheet Rev1.6 ...

Page 4

... Vendor Specific Test Mode ........................................................................................................................................ 36 9 & A ACK ETECT UNCTION SSIGNMENT FOR 9 OLTAGE OLUME ONTROL 9.10 POWER OFF CD F ........................................................................................................................................... 40 UNCTION 9.11 GPIO MART OLUME ONTROL 10. APPLICATION CIRCUIT ................................................................................................................................................ 42 11. MECHANICAL DIMENSIONS........................................................................................................................................ 45 12. ORDERING INFORMATION.......................................................................................................................................... 48 Two-Channel AC’97 2.3 Audio Codec ................................................................................................................................. 36 J ......................................................................................................... 37 ACK ...................................................................................................................................... 39 .................................................................................................................................... 41 iv ALC203 DataSheet Rev1.6 ...

Page 5

... General Description The ALC203 AC'97 codec is a 20-bit DAC and 18-bit ADC full duplex AC'97 2.3 compatible stereo audio codec designed for PC multimedia systems, including host/soft audio and AMR/CNR based designs. The ALC203 incorporates proprietary converter technology to achieve a high SNR, greater than 100 dB, sensing logic for device reporting, and Universal Audio Jack® to improve user experience ...

Page 6

... Block Diagram 3.1 Analog Mixer Block Two-Channel AC’97 2.3 Audio Codec Boost Boost Analog Mixer Diagram 2 ALC203 DataSheet Rev1.6 ...

Page 7

... SP-In data 20-bit SPDIF In 20-bit SPDIF Out 20-bit PCM DVOL DVOL Digital Original ADC Left Right MIC 0 ADC Left DVOL : Digital Volum e Control Digital data path diagram 3 ALC203 DataSheet DAC Line-In CD-In Mixer MIC-In Block ... Analog outputs SPDIF Input SPDIF Output Rev1.6 ...

Page 8

... Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in the figure above. The version number is shown in the location marked ‘V’. Two-Channel AC’97 2.3 Audio Codec AVDD2 AVSS2 42 GPIO0 43 GPIO1 44 JD0 45 46 LLLLLLL 47 SPDIFO Pin Assignments 4 ALC203 DataSheet LINE-IN-R 24 LINE-IN-L 23 MIC2 22 MIC1 21 20 CD-R CD-GND 19 ALC203 CD-L 18 JD1 17 JD2 16 AUX-R 15 TXXXV AUX PHONE ...

Page 9

... Pulled low to use external CMOS input Vt=0.35Vdd, internally pulled high by a 50K 14.318MHz clock source resistor. S/PDIF input / External CMOS input / output Amplifier power down control S/PDIF output Digital output has 12 mA@75Ω driving capability. 5 ALC203 DataSheet Characteristic Definition Total: 13 Pins Rev1.6 ...

Page 10

... Analog input (1.6Vrms) Line-Out Left channel Analog output w/o amplifier Line-Out Right channel Analog output w/o amplifier Headphone Out Left ALC203: Analog output with amplifier / Analog input channel Headphone Out Left ALC203: Analog output with amplifier / Analog input channel Speaker Phone output / Analog output / Third reference voltage output Third Ref ...

Page 11

... SPSR L CC6 CC5 CC4 ALC203 DataSheet ID7 ID6 ID5 ID4 ID3 ID2 X MR5 MR4 MR3 MR2 MR1 MR0 X HPR5 HPR4 HPR3 HPR2 HPR1 HPR0 8000h MM4 MM3 MM2 MM1 MM0 PB3 PB2 PB1 PH4 PH3 PH2 MI4 MI3 MI2 X X NR4 ...

Page 12

... Master Right Volume (MRV[5:0]) in 1.5 dB steps For MRV/MLV: 00h 3Fh 6.1.3 MX04 Headphone Default: 8000h Register 04h controls the headphone (ALC203) output volume. Each step in bits 5:0 and 13:8 corresponds to a 1.5dB increase/decrease in volume, allowing 63 levels of volume, from 000000 to 111111. Bit Type 15 ...

Page 13

... The purpose of this register is to allow the PC Beep signals to pass through the ALC203, eliminating the need for an external system speaker/buzzer. The PC BEEP pin is directly routed (internally hardwired) to the LINE-OUTL & R pins. If the PC speaker/buzzer is eliminated recommended to connect the external speakers at all times so the POST codes can be heard during reset ...

Page 14

... Two-Channel AC’97 2.3 Audio Codec 1: Mute (-∞ dB 11: 29.5 dB (V=30*Vmic-in) +12 dB Gain 0dB gain -34.5dB Gain 1: Mute (-∞ dB) 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain 1: Mute (-∞ dB) 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain 10 ALC203 DataSheet Function Function Function Rev1.6 ...

Page 15

... R/W PCM Right Volume (PRV[4:0]) in 1.5 dB steps For PLV/PRV: Two-Channel AC’97 2.3 Audio Codec Function 1: Mute (-∞ dB) 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain Function 1: Mute (-∞ dB) 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain 11 ALC203 DataSheet Rev1.6 ...

Page 16

... Reserved 11:8 R/W Left Record Gain Select (LRG[3:0]) in 1.5 dB steps 7:4 Reserved 3:0 R/W Right Record Gain Select (RRG[3:0]) in 1.5 dB steps For LRG/RRG: Two-Channel AC’97 2.3 Audio Codec Function Function 1: Mute (-∞ dB) 0Fh +22.5dB 00h 0 dB (No Gain) 12 ALC203 DataSheet Rev1.6 ...

Page 17

... Depth Control (DP[2:0]) 3D effect control DP[2:0] Function 000 0% (off*) 001 12.5% 010 25% 011 37.5 Two-Channel AC’97 2.3 Audio Codec Function 1: Mute (-∞ dB) 0Fh +22.5dB 00h 0 dB (No Gain) Function 0: Off Function DP[2:0] Function 100 50% 101 67.5% 110 75% 111 100% 13 ALC203 DataSheet Rev1.6 ...

Page 18

... This register is used to select a descriptor of 16 word pages between registers MX60 to MX6F. Value used to select vendor specific space to maintain compatibility with AC’97 2.2 vendor specific register. Once PG[3:0] is not 0000b and 0001b, ALC203 will return zero data for ACLINK mixer read command. Two-Channel AC’97 2.3 Audio Codec ...

Page 19

... Power down Mixer (Vref off) 1: Power down Mixer (Vref still on) 1: Power down PCM DAC 1: Power down PCM ADC and input MUX 0: Not yet ready 0: Not yet ready Mixer Verf ACLINK Int CLK HP-OUT Blank: Don’t care 15 ALC203 DataSheet 1: Power down EAPD Rev1.6 ...

Page 20

... VRA Read as 1 (Variable Rate Audio is supported) ID[1:0] depend on the states of pins 46, 45, 44, and 43 when power-on reset or AC97_RESET# is active. Refer to section 9.1 for detailed information on configuration of ID[1:0]. The ALC203 maps DAC slot according to the following table: (default maps to AC’97 spec. rev2.3) DSA[1:0] Left DAC slot # ...

Page 21

... VRA 1: Enable 0: Disable If VRA = 0, the ALC203’s ADC/DAC operate at a fixed 48KHz sampling rate. Otherwise, they operate at a variable sampling rate defined in MX2C and MX32. VRA also controls the write operation of MX2Cand MX32. DRA can be written when (ID=00)&(DSA=00), otherwise it is always 0. ...

Page 22

... MX2C PCM DAC Rate Default: BB80h The ALC203 allows adjustment of the output sample rate. This register is used to adjust the sample rate. By changing the values, sampling rates from 8000 to 48000 can be chosen. Bit Type 15:0 R/W Output Sampling Rate FOSR[15:0] The ALC203 supports the following sampling rates, as required in the PC99/PC2001 design guide. ...

Page 23

... R/W Copyright (COPY) 0: Not asserted 1 R/W Non-Audio Data type (/AUDIO) 0: PCM data 0 R Professional or Consumer format (PRO) 0: Consumer format The ALC203 supports consumer channel status format, so this bit is always 0. The consumer channel status block (bit0~bit31 PRO=0 /AUDIO 8 9 CC0 CC1 16 17 ...

Page 24

... S/PDIF Out Source 00:S/PDIF data is from ACLINK controller 01: Reserved. 10:Directly bypass S/PDIF-In signal to S/PDIF-Out. 11: Reserved. 11 R/W Recorded PCM Data to ACLINK Two-Channel AC’97 2.3 Audio Codec Function 1: Not asserted 1: AC3 or other digital non-audio data 1: professional format Function 1: Locked Function 20 ALC203 DataSheet Rev1.6 ...

Page 25

... This register can be written once only after power on, and is not affected by AC97 cold reset. The system manufacture’s BIOS can set its own sub-vendor ID. The default value FFFFh means this register is implemented and data is not set by BIOS. Two-Channel AC’97 2.3 Audio Codec Function 1: (MIC1+MIC2)/2. 1: Stereo. Function Function 21 ALC203 DataSheet Rev1.6 ...

Page 26

... Clearing this bit by writing “1”, writing “0” to this bit has no effect. 3:1 NA Reserved 0 R Function Information Present, FIP This bit when set to a ‘1’ indicates that the G[4:0], INV, DL[4:0] and ST[2:0] bits are supported and are Read/Write capable. Two-Channel AC’97 2.3 Audio Codec Function Function 1: Inverted. 22 ALC203 DataSheet Rev1.6 ...

Page 27

... Not specified or unknown Other: Not supported This field reports the type of output/input peripheral plugged in the jack after sensing. 7:0 R Always read as 0. Two-Channel AC’97 2.3 Audio Codec Function 06h: Earphone or passive speaker 13h: Mono Microphone 15h: Stereo Line-In 23 ALC203 DataSheet Rev1.6 ...

Page 28

... A low to high transaction will trigger the GPIO interrupt in bit0 of SDATA_IN’s slot-12. 3:2 Reserved 1 R/W GPIO1Primitive Control 0: Set GPIO1 as input pin. 1: Set GPIO1 as output pin. 0 R/W GPIO0 Primitive Control 0: Set GPIO0 as input pin. 1: Set GPIO0 as output pin. Two-Channel AC’97 2.3 Audio Codec Function 1: Enable 1: Enable 1: Enable. 1: Enable. 1: Enable. 1: Enable. 24 ALC203 DataSheet Rev1.6 ...

Page 29

... When MX7A.5=1, MX7A.1=JDS2 GPIO1 Input Status 0: GPIO1 is driven low by external device (input). 1: GPIO1 is driven high by external device (input GPIO0 Input Status 0: GPIO0 is driven low by external device (input). 1: GPIO0 is driven high by external device (input). Two-Channel AC’97 2.3 Audio Codec Function 25 ALC203 DataSheet Rev1.6 ...

Page 30

... The two registers (MX7C Vendor ID1 and MX7E Vendor ID2) contain four 8-bit ID codes. The first three codes have been assigned by Microsoft for Plug and Play definitions. The fourth code is a Realtek assigned code identifying the ALC203. The MX7C Vendor ID1 register contains the value 414Ch, which is the first and second characters of the Microsoft ID code. The ...

Page 31

... Minimum DVDD 3.0 AVDD** 3 Susceptibility Voltage Symbol Minimum V -0. 0.5DVdd IH V 0.9DVdd - 30k Minimum 0 28.8 0 28.8 27 ALC203 DataSheet Typical Maximum 3.3 3.6 5.0 5.5 - +70 +125 4500 V 5000 V Typical Maximum - Dvdd+0.30 - 0.5Dvdd - - - - 0.1DVdd - 50k 100k Typical Maximum - 19.2 -76.0 +- 0.20 - 19.2 -78 ...

Page 32

... Symbol Minimum T 1.0 rst_low T 162.8 rst2clk Trst2clk Trst_low Cold reset timing diagram Symbol Minimum T 1.0 sync_high T 162.8 sync2clk Tsync_high Tsync2clk Warm reset timing diagram 28 ALC203 DataSheet Typical Maximum 3.3 0 0.3 Typical Maximum - - - - Typical Maximum - - - - Units V V Units µs ns Units µs ns Rev1.6 ...

Page 33

... T - sync_period T - sync_high T - sync_low Symbol Minimum Symbol Minimum t 10 setup t 10 hold Symbol Minimum - - TsetupThold BITCLK SYNC Data Output and Input timing diagram 29 ALC203 DataSheet Typical Maximum 12.288 - 81 750 40.7 45 40.7 45 48.0 - 20.8 - 1.3 - 19.5 - Typical Maximum - 15 Typical Maximum - - - - Typical Maximum ...

Page 34

... Trise - din Tfall - din Trise - dout Tfall - dout Signal Rise and Fall timing diagram Symbol Minimum T - s2_pdown slot-1 slot-2 Write to Set PR4 MX26 AC-Link low power mode timing diagram 30 ALC203 DataSheet Typical Maximum - Typical Maximum - 1.0 Ts2_pdown Units Units µs ...

Page 35

... T - off RESET# Tsetup2rst ATE test mode timing diagram 1 CODEC 2 CODEC 55pF 62.5pF 47.5pF 55pF Minimum Typical (h) ( (r) ( (r) (l) ( (f) (l) ( (h) (l) (h) 31 ALC203 DataSheet Typical Maximum - - - 25.0 Hi-Z Toff 3 CODEC 75pF 60pF Maximum 10 55 90% 10% Units CODEC 85pF 62.5pF Units % % Rev1.6 ...

Page 36

... PCBEEP, PHONE cont… Two-Channel AC’97 2.3 Audio Codec 0 C, Dvdd=3.3V ±5%,Avdd=5.0V±5% =25 Minimum - - - - - - - - 10 D/A - A/D - D 19,200 28,800 - -34 4 ALC203 DataSheet Typical Maximum 1.6 - 1.0 - 1.6 - 0.16 - 1.25 - 1.25 - 100 - 100 - - 22,000 100 - 90 - - 19,200 - 28,800 ∞ - - 1 -94.5 1.5 ...

Page 37

... LINE-OUT HP-OUT MONO-OUT Amplifier Maximum Output Power @20Ω load Power Supply Current VA=5.0V VA=3.3V VD=3.3V Power Down Current VA=5.0V / 3.3V VD=3.3V Vrefout/Vrefout2/Vrefout3 Vrefout Drive Current Two-Channel AC’97 2.3 Audio Codec - 200 - 6 - 500 - - - 2. ALC203 DataSheet Ω Ω - Ω 1000 uA 700 uA 4 Rev1.6 ...

Page 38

... RESET# is de-asserted, ALC203 is a consumer of BITCLK. ALC203 should use external 12.288MHz BITCLK as its clock source. Standard secondary mode, ALC203 receive external 12.288MHz clock from BIT-CLK pin. ALC203 E version and later versions do not support secondary mode as pin-45 is re-defined as Jack-Detect pin 0 (JD0) for auto MIC jack sensing. Two-Channel AC’97 2.3 Audio Codec Operation & ...

Page 39

... When the ALC203 receives serial data from the AC97 controller, it samples SDATA_OUT on the falling edge of BIT_CLK. When the ALC203 sends serial data to the AC97 controller, it starts to drive SDATA_IN on the rising edge of BIT_CLK. The ALC203 will return any uninstalled bits or registers with 0 for read operations. The ALC203 also stuffs the unimplemented slot or bit with 0 in SDATA_IN. Note that AC-LINK is MSB-justified. Refer to ‘ ...

Page 40

... It is important to pay special attention to the power down control register (index 26h), especially PR4 (powerdown AC-link). 9.7 Test Mode To provide compatibility with AC’97 rev2.2, the ALC203 will float its digital output pins in both ATE and Vendor-Specific test modes. Please refer to AC’97 rev2.2 section 9.2 for a detailed description of the test modes. ...

Page 41

... The first figure below shows an example of jack detect which can implement this function audio plug is inserted in HP_OUT jack detected as low, and LINE output is normal audio plug is inserted, the ALC203 disables the LINE output, , S/PDIF output, MONO_OUT, HP_OUT. This is useful for some PC applications, such as notebook and home based computers ...

Page 42

... The figure below shows another simple way to implement the jack detect function without using the JD pin of the ALC203 good circuit for motherboard makers only a layout issue and no extra components are needed. Once the HP_OUT jack is plugged in, output signals to LINE_OUT will be isolated, and no signals will be output to the LINE_OUT jack ...

Page 43

... DC Voltage Volume Control The ALC203 has a 32-step internal volume control that is controlled by the DC voltage applied to the ‘DC Vol’ pin (pin-33). The volume control input range is from GND to AVDD. A low-speed counter ramp ADC transmits the DC voltage into a 5-bit volume code to attenuate the master volume (real MX02), headphone volume (real MX04) and mono-out volume (real MX06). ...

Page 44

... The ‘POWER OFF CD’ function describes a state where, after the system has been shut down and a +5V analog power is supplied at VAUX(pin-34), the ALC203 will turn on the CD-IN op and output amplifier possible to design a system which will save op-amp circuitry and bypass CD output directly to the speaker. ...

Page 45

... External Circuitry Two-Channel AC’97 2.3 Audio Codec +3.3VCC 50K 3 2 Vth=2/3 VCC GPIO1 3 2 Vth=1/3 VCC +3.3VCC 50K GPIO0 Vol Up ALC203 External Circuits for Volume Up/Down/Mute 41 ALC203 DataSheet A GPIO1 A B Signal +3. Vol Down B 1.65V 0 1 Mute Vol Down Vol Down ...

Page 46

... To get the best compatibility in hardware design and software driver, any modifications of application circuits should be confirmed by Realtek. +3.3VDD R53 4.7K R55 0 GPIO1 R56 0 GPIO0 Vol-Mute Vol-Down Vol-Up R54 4.7K GPIO Volume Control for ALC203 (No Jack Detection Function) +5VA VREFOUT3 + C19 C20 +3.3VDD HP-OUT-L C23 10u 1u R63 R64 HP-OUT-R C26 ...

Page 47

... AUD-OUT-L AUD-RET Front Panel MIC In Front Panel Connector J15 C63 100P Front Panel Headphone Out Universal Audio Jack(UAJ) Front Panel for ALC203 and ALC250 R32 10K JD1 / FRONT-JACK1-ON + C66 3.3u D4 VREFOUT3-UAJ1 C64 1N4148 FERB HP-OUT-R / UAJ1-IO-R L16 FERB HP-OUT-L / UAJ2-IO-L L17 ...

Page 48

... C34 + 10u 0.1u TORX178/179 can be used without connecting RCA U5 TORX178 4 CASE CASE L7 47uH C47 +5VDD 0.1u +3.3VDD R16 100K R18 10 SPDIF-IN R19 100K 44 ALC203 DataSheet 2 AGND 4 +3.3VDD 6 +5VDD 8 SPDIF-OUT +5VDD C35 C36 + 10u 0.1u Optical Receiver 5 AGND DGND SPDIF-IN DGND R11 10 ...

Page 49

... CHECK 0.354 BSC 0.276 BSC 0.217 0.354 BSC 0.276 BSC 0.217 0.007 0.008 0.011 0.016 BSC 3.5 7 0.018 0.0236 0.030 0.0393 45 ALC203 DataSheet TITLE: LQFP-48 (7.0x7.0x1.6mm) LEADFRAME MATERIAL DOC. NO. VERSION 02 DWG NO. PKGC-065 DATE REALTEK SEMICONDUCTOR CORP. Rev1.6 ...

Page 50

... Realtek sales representatives or agents. Realtek Semiconductor Corp. Headquarters No. 2, Innovation Road II Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com.tw Two-Channel AC’97 2.3 Audio Codec Package Standard product. LQFP-48 ALC203 with Lead (Pb)-Free LQFP-48 package 48 ALC203 DataSheet Status Rev1.6 ...

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