RTL8019 REALTEK, RTL8019 Datasheet

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RTL8019

Manufacturer Part Number
RTL8019
Description
Full-Duplex Ethernet Controller with Plug and Play Function (RealPNP)
Manufacturer
REALTEK
Datasheet

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www.DataSheet4U.com
LS003.6
1995.04.25
Controller with Plug and Play
Realtek Full-Duplex Ethernet
REALTEK SEMI-CONDUCTOR CO., LTD.
INDUSTRIAL PARK, HSINCHU 30077, TAIWAN, R.O.C.
ADVANCE INFORMATION
1F, NO. 11, INDUSTRY E. RD. IX, SCIENCE-BASED
TEL: 886-2-2980098 FAX: 886-2-2980094, 2980097
Function (RealPNP)
TEL:886-35-780211 FAX:886-35-776047
TAIPEI HSIEN, TAIWAN, R.O.C.
3F, NO. 56, WU-KUNG 6 RD.,
RTL8019
HEAD OFFICE
OFFICE

Related parts for RTL8019

RTL8019 Summary of contents

Page 1

... Controller with Plug and Play ADVANCE INFORMATION REALTEK SEMI-CONDUCTOR CO., LTD. 1F, NO. 11, INDUSTRY E. RD. IX, SCIENCE-BASED INDUSTRIAL PARK, HSINCHU 30077, TAIWAN, R.O.C. TEL: 886-2-2980098 FAX: 886-2-2980094, 2980097 LS003.6 1995.04.25 RTL8019 Function (RealPNP) HEAD OFFICE TEL:886-35-780211 FAX:886-35-776047 OFFICE 3F, NO. 56, WU-KUNG 6 RD., TAIPEI HSIEN, TAIWAN, R.O.C. ...

Page 2

... REGISTER DESCRIPTIONS 5.1. Group 1: NE2000 Registers 5.1.1. Register Table 5.1.2. Register Functions 5.1.2.1. NE2000 Compatible Registers 5.1.2.2. RTL8019 Defined Registers 5.2. Group 2: Plug and Play (PnP) Registers 5.2.1. Card Control Registers 5.2.2. Logical Device Control Registers 5.2.3. Logical Device Configuration Registers 6 ...

Page 3

... Supports BROM disable command to release memory after remote boot m Use two 8K or single 32K byte SRAM as local buffer memory m Use 9346 (64*16-bit EEPROM) to store resource configurations and ID parameters m Capable of programming blank 9346 on board for manufacturing convenience m Support 4 diagnostic LED pins with programmable outputs LS003.6 1995.04.25 ADVANCE INFORMATION 3 RTL8019 ...

Page 4

... The RTL8019 is a highly integrated Ethernet Controller which offers a simple solution to implement a Plug and Play NE2000 compatible adapter with full-duplex and power down features. With the three level power down control features, the RTL8019 is made ideal choice of the network device for a GREEN PC system. The full-duplex function enables simultaneously transmission and reception on the twisted-pair link to a full-duplex Ethernet switching hub ...

Page 5

... INT3 [IRQ4] 8 INT2 [IRQ3] 9 INT1 10 INT0 [IRQ2/9] 11 SA0 12 SA1 13 SA2 14 SA3 15 GND LS003.6 1995.04.25 RTL8019 5 ADVANCE INFORMATION RTL8019 65 MA12 [PNP] 64 MA13 [JP] 63 LED2 [LED_TX] [MCSB] [LED_RX] [LED_CRS] 62 LED1 [LED_COL][LED_LINK] 61 LED0 60 LEDBNC 59 TPIN+ 58 TPIN- 57 VDD 56 RX+ 55 RX- 54 CD+ 53 CD- ...

Page 6

... IRQ11, IRQ10, IRQ5, IRQ4, IRQ3, IRQ2/9 respectively. Only one line is selected to reflect the interrupt requests at one time. All other lines are tri-stated. The RTL8019 also uses these pins as inputs to monitor the actual state of the corresponding interrupt lines on ISA bus. The result is recorded in the INTR register, which may be used by software to detect interrupt conflict ...

Page 7

... When high, this pin selects jumper mode. When low, it selects jumperless modes (including RT jumperless and Plug and Play). I When it is high in jumperless mode (i.e. JP=low), the RTL8019 is forced into Plug and Play mode regardless of the contents of 9346. The following pins are don't care in jumperless mode (JP=low). I Select BROM size and base address ...

Page 8

... Name Type O This pin goes high when RTL8019's medium type is set to 10Base2 mode or auto-detect mode with link test failure. Otherwise, this pin is low. This pin can be used to control the power of the DC convertor for CX MAU and connected to an LED to indicate the used medium type. ...

Page 9

... Register Descriptions The registers in RTL8019 can be roughly divided into two groups by their address and functions -- one for NE2000, the other for Plug and Play (PnP). 5.1. Group 1: NE2000 Registers This group includes 4 pages of registers which are selected by bit PS0 & PS1 in the CR register. ...

Page 10

... FB21 FB20 FB31 FB30 FB29 FB28 FB39 FB38 FB37 FB36 FB47 FB46 FB45 FB44 FB55 FB54 FB53 FB52 FB63 FB62 FB61 FB60 10 ADVANCE INFORMATION RTL8019 Bit 3 Bit 2 Bit 1 Bit 0 RD0 TXP STA STP A11 A10 A9 A8 A11 A10 A9 A8 A11 A10 A9 ...

Page 11

... PL0 BSELB - PNP FUDUP LEDS1 LEDS0 - - - - Reserved CSN7 CSN6 CSN5 CSN4 HLT7 HLT6 HLT5 HLT4 Reserved INT7 INT6 INT5 INT4 11 ADVANCE INFORMATION RTL8019 Bit 3 Bit 2 Bit 1 Bit 0 RD0 TXP STA STP A11 A10 A9 A8 A11 A10 A9 A8 A11 A10 SEP ATD ...

Page 12

... PS1 PS0 Register Page RD2 RD1 RD0 Not allowed Remote Read Remote Write Send Packet Abort/Complete remote DMA STA STP Function 1 0 Start Command 0 1 Stop Command Description 12 ADVANCE INFORMATION RTL8019 Remark NE2000 compatible NE2000 compatible NE2000 compatible RTL8019 Configuration Function ...

Page 13

... This bit must be set to zero. NIC only supports dual 16-bit DMA mode. POWER BOS Byte Order Select 0: MS byte placed on MD15-8 and LS byte on MD7-0. (32xxx,80x86 byte placed on MD7-0 and LS byte on MD15-8. (680x0) 0 WTS Word Transfer Select 0: byte-wide DMA transfer 1: word-wide DMA transfer LS003.6 1995.04.25 ADVANCE INFORMATION Description 13 RTL8019 ...

Page 14

... Description LB1 LB0 Mode Conditions CRC Logic Activities CRC Bit Mode CRC Generator 0 normal enabled 1 normal disabled 0 loopback enabled 1 loopback disabled Description 14 ADVANCE INFORMATION Remark Normal Operation Internal Lookback External Lookback External Lookback CRC Checker enabled enabled disabled enabled RTL8019 ...

Page 15

... The Page Stop register sets the stop page address of the receive buffer ring. BNRY: Boundary Register (03H; Type=R/W in Page0) This register is used to prevent overwrite of the receive buffer ring typically used as a pointer indicating the last receive buffer page the host has read. LS003.6 1995.04.25 ADVANCE INFORMATION Description Description 15 RTL8019 ...

Page 16

... Current Page Register (07H; Type=R/W in Page1) This register points to the page address of the first receive buffer page to be used for a packet reception. MAR0-7: Multicast Address Register (08H - 0FH; Type=R/W in Page1) These registers provide filtering bits of multicast addresses hashed by the CRC logic. LS003.6 1995.04.25 ADVANCE INFORMATION 16 RTL8019 ...

Page 17

... RTL8019 Defined Registers Page 0 (PS1=0, PS0=0) Two registers are defined to contain the RTL8019 chip ID. No. Name 0AH 8019ID0 0BH 8019ID1 Page 3(PS1=1, PS0=1) Page3 Power Up Values before loading jumper states and 9346 contents No. Name Type 00H CR R/W 01H 9346CR ...

Page 18

... Not used 3 JP This bit reflects the state of JP input. It, when set, indicates the RTL8019 is in jumper mode. 2 BNC When set, this bit indicates that the RTL8019 is using the 10Base2 thin cable as its networking medium. This bit will be set in the following 2 cases: ...

Page 19

... This bit's power-up initial value is 1 and may be modified by software if EEM1=EEM0=1 in 9346CR register. 6-4 IRQS2-0 IRQ Select : These 3 bits select one of INT7-0 to reflect the RTL8019's interrupt request status. All unselected interrupt lines will be tri-stated. 3-0 IOS3-0 Select I/O base address. LS003.6 1995 ...

Page 20

... BS4-0 These bits select the BROM size & memory base address. The RTL8019 supports a special BROM mode: page mode. In page mode, the BROM always occupies 16K-byte host memory space. However the actual BROM size can bytes. The BROM is divided into several 16K-byte pages. The power on boot page is set to page 0 and the program in page 0 is responsible to select the other pages by the BPAGE register and load their programs ...

Page 21

... LS003.6 1995.04.25 ADVANCE INFORMATION BROM size BA14 BA15 16K high 32K SA14 64K SA14 21 RTL8019 high high SA15 ...

Page 22

... Symbol 7 PNP This bit is negligible in jumper mode. In jumperless mode it, when set, indicates the RTL8019 is operating in Plug and Play mode. This bit is set when the PNP pin is high or the PNP bit in 9346 is set in jumperless mode. 6 FUDUP When this bit is set, RTL8019 is set to the full-duplex mode which enables simultaneously transmission and reception on the twisted-pair link to a full- duplex Ethernet switching hub ...

Page 23

... HLTCLK: Halt Clock Register (09H; Type=W) This is the only active one of Group1 registers when RTL8019 is inactivated. Writing to this register is invalid if RTL8019 is not in power down mode. (i.e. If PWRDN bit in CONFIG3 register is zero.) The data written to this register determines the RTL8019's power down mode. ...

Page 24

... Wake[CSN] command. The CSN value written to this register will also be recorded to the CSNSAV register located at PnP register index F5H and Group 1 Page3 offset 08H. R 00H (Only one logical device in RTL8019). 24 ADVANCE INFORMATION RTL8019 ...

Page 25

... BROM base address bits[23:16] 41H BROM base address bits[15:0] 42H Memory Control Note: The BROM size of RTL8019 is determined by the 9346 contents but not the memory configuration registers. I/O Configuration Registers Index Name 60H I/O base address bits[15:8] 61H I/O base address bits[7:0] LS003 ...

Page 26

... F3H CONFIG3 F4H - F5H CSNSAV F6H Vendor Control 6. Functional Descriptions 6.1. RTL8019 Configuration Modes The RTL8019 supports 3 configuration modes: jumper, RT jumperless, and PnP. JP Pin High Low Low Low P.S. "*" denotes don't care. LS003.6 1995.04.25 Definition Read/write value indicating a selected interrupt level. ...

Page 27

... RT initiation key is supported in all configuration modes while the PnP initiation key is only supported in the PnP mode. By using the RT initiation key, the software can put RTL8019 to the PnP Config state and access the logical device configuration registers even in the jumper and RT jumperless modes ...

Page 28

... The Plug and Play logic is quiescent on power up and must be enabled by software. This is done by a predefined series of writes (32 I/O writes) to the ADDRESS port, which is called the initiation key. The write sequence is decoded by RTL8019. If the proper series of I/O writes is detected, then the Plug and Play auto-configuration ports are enabled. The write sequence will be reset and must be issued from the beginning if any data mismatch occurs ...

Page 29

... Wait for next read from serial isolation register Leave SD [7:0] in high impedance After I/O read completes fetch next ID bit from serial identifier yes 29 ADVANCE INFORMATION no Leave SD [7:0] in high-impedance no SD[1:0]="01" yes no SD[1:0]="10" yes ID=0 other card ID=1 State Sleep RTL8019 ...

Page 30

... The above sequence is repeated for the entire 72-bit serial identifier. LS003.6 1995.04.25 Vendor ID Byte 1 Byte 0 Byte 3 Byte 2 7:0 7:0 7:0 7:0 Figure 2. Shifting of Serial Identifier 30 ADVANCE INFORMATION RTL8019 Byte 1 Byte 0 7:0 7:0 Shift ...

Page 31

... All other results are assumed "0". During the first 64 bits, software generates a checksum using the received data. The checksum is compared with the checksum read back in the last 8 bits of the sequence. LS003.6 1995.04. Figure 3. Checksum LFSR 31 ADVANCE INFORMATION RTL8019 Shift out ...

Page 32

... NOTE: The software must delay 1 msec prior to starting the first pair of isolation reads, and must wait 250 sec between each subsequent pair of isolation reads. This delay gives the ISA card time to access information from possibly very slow storage devices. LS003.6 1995.04.25 ADVANCE INFORMATION 32 RTL8019 ...

Page 33

... Wait for Key 4. The Reset CSN commands include PnP Reset CSN and RT Reset CSN commands. The former sets all ISA PnP cards' CSNs to zero while the latter only sets RTL8019 PnP cards' CSNs to zero. Both commands do not cause a state transition. ...

Page 34

... There is a required 2 msec delay from either a RSTDRV or a PnP Reset command to any Plug and Play port access to allow a card to load initial configuration information from a non-volatile device, which is 9346 for RTL8019. Cards in the Wait for Key state do not respond to any access to their auto-configuration ports until the initiation key is detected ...

Page 35

... Bit 6 CONFIG1 * IRQS2 CONFIG2 PL1 PL0 CONFIG3 PNP FUDUP P.S. '*' denotes don't care. Example : Plug and Play Resource Data for RTL8019 (Total 73+5 bytes) TAG Plug and Play Version Number Item byte PnP version Vendor version LS003.6 1995.04.25 Contents Power-up initial value of Page3 and PnP ...

Page 36

... This example uses 16k-byte BROM. 09H 00H 40H 00H 0CH C0H 0DH 00H 40H 40H 00H Length: fixed 79H 2's complement of the sum of all the above resource data i.e. 2's complement of (0AH+10H+10H+.......+79H) 36 ADVANCE INFORMATION RTL8019 37 bytes 7 bytes 5 bytes if given 8 bytes 4 bytes 12 bytes 2 bytes ...

Page 37

... Local Memory Bus Control The local memory bus of RTL8019 is shared by the SRAM, BROM & 9346 EEPROM. The following diagram demonstrates their connection relationship. RTL8019 MD7-0 MRDB MWRB EECS MCSB BCSB BROM D7-0 MD7-0 CE BCSB LS003.6 1995.04.25 MA3-1 MA13-2 MA13-1 ...

Page 38

... H L DIS DIS BUS H L DIS DIS DIS L * DIS DIS BUS L * DIS DIS DIS 38 ADVANCE INFORMATION RTL8019 SRAM Comments 8K#2 32K EN EN read BROM EN EN idle DIS DIS access 9346 DIS BUS read SRAM#1 BUS BUS read SRAM#2 DIS BUS write SRAM#1 ...

Page 39

... LED_TX: Tx LED (2) LED_RX: Rx LED LS003.6 1995.04.25 Power On LED=low Transmitting Packet? Yes + LED=high for (100 10 LED=low for ( Power On LED=low Receiving Packet? Yes + LED=high for (100 10 LED=low for ( ADVANCE INFORMATION RTL8019 No No ...

Page 40

... LED_CRS=LED_TX+LED_RX: Carrier Sense LED (4) LED_COL: Collision LED LS003.6 1995.04.25 ADVANCE INFORMATION Power On LED=low Packet? Yes + LED=high for (100 10 LED=low for ( Power On LED=high Collision (except Heartbeat)? Yes + LED=low for ( RTL8019 No No ...

Page 41

... LED_CRS 6.6. Loopback Diagnostic Operation 6.6.1. Loopback operation The RTL8019 provides 3 loopback modes. By loopback test, we can verify the integrity of data path, CRC logic, address recognition logic and cable connection status. Mode 1: Loopback through the NIC (LB1=0, LB0=1 in TCR). The NRZ data is not transmitted to the SNI but instead it's loopbacked to the NIC's Rx deserializer ...

Page 42

... Select a loopback mode (e.g. mode 2) to test A. To test CRC generator s set RCR=00h to accept physical packet s set PAR0-5 to accept packet s set TCR=04h (CRC enabled) s set DCR=40h (8-bit slot) or 43h (16-bit slot) s clear ISR packet s check CRC bytes in FIFO after loopback LS003.6 1995.04.25 ADVANCE INFORMATION 42 RTL8019 ...

Page 43

... B. Wrong physical destination address s set RCR=00h to accept physical packet s set PAR0-5 to reject packet s set TCR=04h (CRC enabled) s set DCR=40h (8-bit slot) or 43h (16-bit slot) s clear ISR packet s check ISR after loopback Expected: ISR=02h (packets rejected response) LS003.6 1995.04.25 ADVANCE INFORMATION 43 RTL8019 ...

Page 44

... If MAU not connected, get TSR=53h (Carrier sense is lost during transmission and CD heartbeat fails.). C. 10BaseT with link test disabled RTL8019 disables link test in this case, so cable OK or FAIL doesn't affect TSR; get TSR=03h. D. Auto-detection (10BaseT with link test enabled) RTL8019 automatically switches from 10BaseT to 10Base 2 if the twisted-pair wire is not connected (10BaseT link test fails). If twisted-pair wire OK, get TSR=03h (Tx OK) & ...

Page 45

... Note 3: Apply only to IOCHRDY, IOCS16B LS003.6 1995.04.25 ADVANCE INFORMATION Min. Typ. Max. 0.8 2.0 0.4 0.6 3.0 3.5 0.4 0.6 3.5 4.0 0.6 50 100 150 - RTL8019 Unit Conditions Iol=16mA, Note 1 V Ioh=8mA, Note 1 V Iol=4mA, Note 2 V Ioh=4mA, Note 2 V Iol=24mA, Note ...

Page 46

... IOWB when no wait state insertion is needed. T5 Read data valid to IOCHRDY high when wait state is needed T6 Read data hold after IORB rising edge T7 Write data setup to IOWB rising edge T8 Write data hold from IOWB rising edge LS003.6 1995.04. Parameter Min ADVANCE INFORMATION RTL8019 Typ. Max. Unit ...

Page 47

... T3 MRDB or MWRB low width T4 Read data setup to MRDB high T5 Read data hold from MRDB rising edge T6 Write data setup to MWRB rising edge T7 Write data hold from MWRB rising edge LS003.6 1995.04. Parameter Min ADVANCE INFORMATION RTL8019 T1 Typ. Max. Unit 100 ...

Page 48

... IOCHRDY low width T3 SMEMRB low to BA14-21 valid T4 SMEMRB low to BCSB valid T5 BA14-21 hold from SMEMRB rising edge T6 BCSB hold from SMEMRB rising edge T7 Read data hold from SMEMRB rising edge LS003.6 1995.04. Parameter Min. 48 ADVANCE INFORMATION RTL8019 Typ. Max. Unit 30 ns 200 ...

Page 49

... This document has been carefully checked and is believed to be accurate. However REALTEK Semiconductor Co., Ltd. assumes no responsibility for inaccuracies. LS003.6 1995.04. Parameter Min. 49 ADVANCE INFORMATION A0 D1 D15 D14 T6 Typ. Max. Unit 3.2 s 3.2 s 3.0 s 3 RTL8019 D0 ...

Page 50

... TITLE : 100L QFP ( 14x20 mm**2 ) FOOTPRINT 4.8 mm APPROVE CHECK ¡Ð 0.10 0¢X ¡Ð 12¢X REALTEK SEMI-CONDUCTOR CO., LTD 50 ADVANCE INFORMATION RTL8019 PACKAGE OUTLINE DRAWING LEADFRAME MATERIAL: DWG NO. REV NO. SCALE Ricardo Chen DATE SHT NO ...

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