RTL8100C REALTEK, RTL8100C Datasheet
RTL8100C
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RTL8100C Summary of contents
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... RTL8100C & RTL8100CL SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT DATASHEET Rev. 1.06 05 November 2004 Track ID: JATR-1076-21 ...
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... USING THIS DOCUMENT This document provides detailed user guidelines to achieve the best performance when implementing a 2-layer board PC design with the RTL8100C or RTL8100CL Single-Chip Fast Ethernet Controller with Power Management Control. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide ...
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... GENERAL DESCRIPTION...............................................................................................................1 2. FEATURES..........................................................................................................................................2 3. BLOCK DIAGRAM............................................................................................................................3 4. PIN ASSIGNMENTS ..........................................................................................................................4 4.1. RTL8100C (QFP) & RTL8100CL (LQFP).....................................................................................4 5. PIN DESCRIPTION............................................................................................................................5 5. OWER ANAGEMENT 5.2. PCI I ................................................................................................................................6 NTERFACE 5.3. EPROM/EEPROM I 5. .....................................................................................................................................8 OWER INS 5.5. LED I ...............................................................................................................................8 NTERFACE 5. TTACHMENT NIT 5. EST AND THER INS 5. EGISTER ESCRIPTIONS 5 ...
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... OUNTER 5.32 ALSE ARRIER ENSE 5.33 EST EGISTER 5.34. RX_ER C (O OUNTER 5.35 ONFIGURATION 5.36 ONFIG ONFIGURATION 5.37. EEPROM (93C46) C 5.38. RTL8100C(L) EEPROM R 5.39. EEPROM P M OWER 6. PCI CONFIGURATION SPACE REGISTERS.............................................................................38 6.1. PCI C ONFIGURATION 6.2. PCI C ONFIGURATION 6.3. PCI C ONFIGURATION 6. EFAULT ALUES AFTER 6.5. PCI P M OWER ANAGEMENT 6 ...
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... APPLICATION INFORMATION ..................................................................................................61 10. MECHANICAL DIMENSIONS ......................................................................................................62 10.1. RTL8100C 128-P IN 10.2. N RTL8100C 128-P OTES FOR 10.3. RTL8100CL 128-P IN 10.4. N RTL8100CL 128-P OTES FOR 11. ORDERING INFORMATION ........................................................................................................65 Single-Chip Fast Ethernet Controller ......................................................................................................................51 .........................................................................................................54 ...................................................................................................................54 ...................................................................................................................55 QFP...............................................................................................................62 QFP ............................................................................................63 IN LQFP..........................................................................................................64 LQFP .......................................................................................65 IN iii RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Table 27. Basic Mode Status Register .........................................................................................................29 Table 28. Auto-Negotiation Advertisement Register...................................................................................30 Table 29. Auto-Negotiation Link Partner Ability Register..........................................................................31 Table 30. Auto-Negotiation Expansion Register .........................................................................................32 Table 31. Disconnect Counter......................................................................................................................32 Table 32. False Carrier Sense Counter ........................................................................................................32 Table 33. NWay Test Register......................................................................................................................33 Single-Chip Fast Ethernet Controller List of Tables ii RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Table 34. RX_ER Counter ...........................................................................................................................33 Table 35. CS Configuration Register...........................................................................................................33 Table 36. Config5. Configuration Register 5...............................................................................................34 Table 37. EEPROM (93C46) Contents........................................................................................................35 Table 38. RTL8100C(L) EEPROM Registers Summary.............................................................................37 Table 39. EEPROM Power Management Registers Summary....................................................................37 Table 40. PCI Configuration Space Table ...................................................................................................38 Table 41. PCI Configuration Space Functions ............................................................................................40 Table 42. PCI Configuration Space Status...................................................................................................41 Table 43 ...
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... Figure 13. Target Initiated Termination - Retry...........................................................................................58 Figure 14. Target Initiated Termination - Disconnect..................................................................................59 Figure 15. Target Initiated Termination - Abort...........................................................................................59 Figure 16. Master Initiated Termination – Abort.........................................................................................60 Figure 17. Parity Operation - One Example ................................................................................................60 Figure 18. Application Information .............................................................................................................61 Single-Chip Fast Ethernet Controller List of Figures iv RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... PCI Vital Product Data (VPD) is also supported to provide hardware identifier information. The information may consist of part number, serial number, OEM brand name, and other detailed information. To provide cost down support, the RTL8100C(L) is capable of using a 25MHz crystal or OSC as its internal clock source. ...
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... Packet*, LinkChg, and Microsoft® wake-up frame) * Third-party brands and names are the property of their respective owners. Note: The QFP package model number is RTL8100C. The LQFP package model number is RTL8100CL. Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL Supports 4 Wake-On-LAN (WOL) signals ...
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... Wander Correction MLT-3 3 Level Comparator to NRZI ck Serial to Slave Parrallel PLL Data Control Voltage Figure 1. Block Diagram 3 RTL8100C & RTL8100CL LED Driver Transmit/ Receive MII Logic Interface Interface RXD Descrambler RXC 25M TXD TXC 25M Link Pulse 10M Output Waveform Shaping Receive Low Pass Filter ...
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... Pin Assignments 4.1. RTL8100C (QFP) & RTL8100CL (LQFP) 1 TX+ 2 TX- 3 AVDD33 4 GND 5 RX+ 6 RX- 7 AVDD33 8 CTRL25 AVDD25 GND AVDD33(REG) 21 GND ISOLATEB INTAB 26 VDD33 27 PCIRSTB 28 PCICLK 29 GNTB 30 REQB 31 PMEB 32 VDD25 33 AD31 34 AD30 ...
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... Table 1. Power Management/Isolation Interface Pin No Description 31 Power Management Event. Open drain, active low. Used by the RTL8100C(L) to request a change in its current power management state and/or to indicate that a power management event has occurred. 23 Isolate Pin: Active low. Isolates the RTL8100C(L) from the PCI bus. The RTL8100C(L) does ...
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... Grant. This signal is asserted low to indicate to the RTL8100C(L) that the central arbiter has granted ownership of the bus to the RTL8100C(L). This input is used when the RTL8100C(L) is acting as a bus master. 30 Request. The RTL8100C(L) will assert this signal low to request the ownership of the bus from the central arbiter. ...
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... As a target, PAR is asserted during read data phases. 70 Parity Error. When the RTL8100C(L) is the bus master and a parity error is detected, the RTL8100C(L) asserts both the SERR bit in ISR, and Configuration Space command bit 8 (SERRB enable). Next, it completes the current data burst transaction, then stops operation and resets itself ...
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... Aux. Power Detect. This pin is used to notify the RTL8100C(L) of the existence of Aux. power (only during initial power-on). This pin should be pulled high to the auxiliary power (5VPM or 3VAUX) via a resistor to detect the Aux. power. Doing so will enable wakeup support from ACPI D3 cold or APM power-down ...
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... This signal is used to request starting (or speeding up) of the clock. CLKRUN also indicates the clock status. CLKRUN is an open drain output as well as an input. The RTL8100C(L) requests the central resource to start, speed up, or maintain the interface clock by the assertion of CLKRUN. For the host system S/T/S signal. The ...
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... Register Descriptions The RTL8100C(L) provides the following set of operational registers mapped into PCI memory space or I/O space. Offset R/W 0000h R/W 0001h R/W 0002h R/W 0003h R/W 0004h R/W 0005h R/W 0006h-0007h - 0008h R/W 0009h R/W 000Ah R/W 000Bh R/W 000Ch R/W 000Dh R/W 000Eh R/W 000Fh R/W 0010h-0013h R/W 0014h-0017h R/W 0018h-001Bh R/W 001Ch-001Fh R/W 0020h-0023h R/W 0024h-0027h R/W 0028h-002Bh R/W 002Ch-002Fh R/W 0030h-0033h ...
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... Power Management CRC register 0 for wakeup frame 0. CRC1 Power Management CRC register 1 for wakeup frame 1. CRC2 Power Management CRC register 2 for wakeup frame 2. CRC3 Power Management CRC register 3 for wakeup frame 3. CRC4 Power Management CRC register 4 for wakeup frame 4. 11 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... This bit set to 1 indicates that the received packet length is smaller than 64 bytes ( i.e. media header + data + CRC < 64 bytes ) LONG Long Packet. This bit set to 1 indicates that the size of the received packet exceeds 4k bytes. 12 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Transmit Status Register (TSD0-3)(Offset 0010h-001Fh, R/W) The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8100C(L) when the Transmit Byte Count (bits 12-0) in the corresponding Tx descriptor is written not affected when software writes to these bits. These registers are only permitted to be written via double-word access. ...
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... That is, when TSD<TUN>=1, TSD<TOK>=0 and ISR<TOK>=1 (or ISR<TER>=1). OWN OWN. The RTL8100C(L) sets this bit to 1 when the Tx DMA operation of this descriptor has completed. The driver must set this bit to 0 when the Transmit Byte Count (bits 0-12) is written. The default value is 1. SIZE Descriptor Size ...
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... Command Register (Offset 0037h, R/W) This register is used for issuing commands to the RTL8100C(L). These commands are issued by setting the corresponding bits for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here. Bit R/W 7 R/W 3 R/W 2 ...
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... Enable 0: Disable Table 14. Interrupt Status Register Symbol Description SERR System Error. Set to 1 when the RTL8100C(L) signals a system error on the PCI bus. TimeOut Time Out. Set to 1 when the TCTR register reaches the value of the TimerInt register. LenChg Cable Length Change. ...
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... R/W 3 R/W 2 R/W 1 R/W 0 R/W 5.15. Transmit Configuration Register (Offset 0040h-0043h, R/W) This register defines the Transmit Configuration for the RTL8100C(L). It controls such functions as Loopback, programmable InterFrame Gap, Fill and Drain Thresholds, and maximum DMA burst size. Bit R 30~26 R Single-Chip Fast Ethernet Controller Symbol Description FOVW Rx FIFO Overflow ...
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... Reserved. CLRABT Clear Abort. Setting this bit to 1 causes the RTL8100C(L) to retransmit the packet at the last transmitted descriptor when this transmission was aborted, Setting this bit is only permitted in the transmit abort state. 18 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev ...
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... Receive Configuration Register (Offset 0044h-0047h, R/W) This register is used to set the receive configuration for the RTL8100C(L). Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here. Bit R/W 31-28 - 27-24 R/W 23- R/W 16 R/W Single-Chip Fast Ethernet Controller Table 16. Receive Configuration Register ...
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... Rx buffer if this packet has not been completely moved into the Rx buffer and the transfer has arrived at the end of the Rx buffer. 1: The RTL8100C(L) will keep moving the rest of the packet data into the memory immediately after the end of the Rx buffer, if this packet has not been completely moved into the Rx buffer and the transfer has arrived at the end of the Rx buffer ...
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... Accept 0: Reject AB Accept Broadcast packets. 1: Accept 0: Reject AM Accept Multicast packets. 1: Accept 0: Reject APM Accept Physical Match packets. 1: Accept 0: Reject AAP Accept All Packets. Set accept all packets with a physical destination address. 1: Accept 0: Reject 21 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Command Register (Offset 0050h, R/W) This register is used for issuing commands to the RTL8100C(L). These commands are issued by setting the corresponding bits for the function. A warm software reset along with individual reset and enable/disable for transmitter and receiver are also provided. ...
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... Driver loaded 0: Driver not loaded When the command register bits IOEN, MEMEN, and BMEN of the PCI configuration space are written, the RTL8100C(L) will clear this bit automatically. LWAKE active mode: The LWACT bit and LWPTN bit in CONFIG4 register are used to program the LWAKE pin’s output signal. Depending on the combination of these two bits, there may be 4 choices of LWAKE signal, i ...
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... Flow control is enabled in full-duplex mode only. The default value comes from the 93C46. - Reserved. Aux_Status Aux. Power present Status. 1: Aux. Power is present 0: Aux. Power is absent The value of this bit is fixed after each PCI reset. 24 RTL8100C & RTL8100CL Datasheet Remote TXFCE/LdTXFCE NWAY FLY mode R/O NWAY mode only R/W No NWAY R/W ...
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... Set when the RTL8100C(L) sends a pause packet. Reset when the RTL8100C(L) sends a timer done packet. RXPF Receive Pause Flag. Set when the RTL8100C( backoff state because a pause packet was received. Reset when the pause state is cleared. Table 21. CONFIG 3: Configuration Register3 ...
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... MISC + CRC LinkUp Link Up. This bit is valid when the PWEn bit of CONFIG1 register is set. The RTL8100C(L), when in an adequate power state, will assert the PMEB signal to wakeup the operating system when the cable connection is re-established. - Reserved ...
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... The RTL8100C(L) supports wake-up frames, each with masked bytes selected from offset The RTL8100C(L) supports wake-up frames, each with a 16-bit CRC algorithm for MS Wakeup Frame support. The low byte of the 16-bit CRC should be placed in the corresponding CRC register, and the high byte of the 16-bit CRC should be placed in the corresponding LSB CRC register ...
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... Note: The following is true when MulERINT=0 (bit17, RCR). When MulERINT=1, any received packet invokes an early interrupt according to the MISR[11:0] setting in Early Mode. If the received packet data is not a familiar protocol (IPX, IP, NDIS, etc.) to the RTL8100C(L), RCR<ERTH[3:0]> will not be used to transfer data in early mode. This register will be written to the received data length in order to make an early Rx interrupt for the unfamiliar protocol ...
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... Description/Usage 1: Enable 100Base-T4 support 0: Disable 100Base-T4 support 0: Disable 100Base-TX full-duplex support 0: Disable 100Base-TX half-duplex support 1: Enable 10Base-T full-duplex support 0: Disable 10Base-T full-duplex support 1: Enable 10Base-T half-duplex support 0: Disable 10Base-T half-duplex support 29 RTL8100C & RTL8100CL Datasheet Default/Attribute ...
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... Binary encoded selector supported by this node. Currently only CSMA/CD <00001> is specified. No other protocols are supported. 30 RTL8100C & RTL8100CL Datasheet Default/Attribute - ...
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... Link Partner's binary encoded node selector. Currently only CSMA/CD <00001> is specified. 31 RTL8100C & RTL8100CL Datasheet Default/Attribute ...
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... This 16-bit counter increments by 1 for every disconnect event. It rolls over when full cleared to zero by a read command. Table 32. False Carrier Sense Counter Description/Usage This 16-bit counter increments by 1 for each false carrier event cleared to zero by a read command. 32 RTL8100C & RTL8100CL Datasheet Default/Attribute - ...
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... Assertion of this bit forces the disconnect function to be bypassed. Reserved. This bit indicates the status of the connection. 1: Valid connected link detected 0: Disconnected link detected Assertion of this bit configures the LED1 pin to indicate connection status. Reserved. Bypass Scramble. 33 RTL8100C & RTL8100CL Datasheet Default/Attribute - Default/Attribute ...
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... LANWake signal enable/disable. 1: Enable LANWake signal 0: Disable LANWake signal PME_STS PME_Status bit. Always sticky/can be reset by PCI RST# and software. 1: The PME_Status bit may be reset by PCI reset or by software 0: The PME_Status bit may only be reset by software 34 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... RTL8100C(L) supports flow control (IEEE 802.3x). In this case, Bit 10=1 in the Auto-negotiation Advertisement Register (offset 66h-67h). If Bit 1=1 this means the local RTL8100C(L) does not support flow control. In this case, Bit 10=0 in Auto-negotiation Advertisement. This is because some NWay switching hubs randomly send flow control pause packets if the link partner supports NWay flow control ...
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... PHY Parameter 1-U for RTL8100C(L). Operational registers of the RTL8100C(L) are from 78h to 7Bh. Reserved. Do not change this field without Realtek approval. PHY Parameter 2-U for RTL8100C(L). Operational register of the RTL8100C(L) is 80h. Reserved. Do not change this field without Realtek approval. Do not change this field without Realtek approval. ...
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... RTL8100C(L) EEPROM Registers Summary Table 38. RTL8100C(L) EEPROM Registers Summary Offset Name Type * 00h-05h IDR0 – IDR5 R/W 51h CONFIG0 52h CONFIG1 58h MSRBMCR 63H 59h CONFIG3 5Ah CONFIG4 R/W ** 78h-7Bh PHY1_PARM R/W ** 7Ch-7Fh TW1_PARM R/W TW2_PARM ** 80h PHY2_PARM R/W * D8h CONFIG5 R/W Registers marked ' can be written only if bits EEM1:0 = [1:1] ...
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... RESERVED SVID6 SVID5 SVID4 SVID14 SVID13 SVID12 SMID6 SMID5 SMID4 SMID14 SMID13 SMID12 - - - RESERVED ILR6 ILR5 ILR4 RTL8100C & RTL8100CL Bit4 Bit3 Bit2 Bit1 BMEN MEMEN - - BMEN MEMEN FBTBEN SERREN - ...
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... PCI Configuration Space Functions The PCI configuration space is intended for configuration, initialization, and catastrophic error handling functions. The functions of the RTL8100C(L)’s configuration space are described below. VID: Vendor ID. This field defaults to a value of 10ECh (Realtek Semiconductor’s PCI Vendor ID). ...
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... PERRSP Parity Error Response. 1: The RTL8100C(L) will assert the PERRB pin on detection of a data parity error when acting as the target, and will sample the PERRB pin as the master 0: Any detected parity error is ignored and the RTL8100C(L) continues normal operation Parity checking is disabled after hardware reset (RSTB). ...
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... When set indicates that the RTL8100C(L) master transaction was terminated due to a target abort. Writing a 1 clears this bit STABT Signaled Target Abort. Set to 1 whenever the RTL8100C(L) terminates a transaction with target abort. Writing a 1 clears this bit to 0. 10-9 DST1-0 Device Select Timing. ...
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... Read back as 0. This allows the PCI bridge to determine that the RTL8100C(L) requires 256 bytes of IO space Reserved. 0 IOIN IO Space Indicator. Read only. Set the RTL8100C(L) to indicate that it is capable of being mapped into IO space. Single-Chip Fast Ethernet Controller Table 43. Base IO Address 42 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... MEMIN Memory Space Indicator. Read only. Set the RTL8100C(L) to indicate that it is capable of being mapped into memory space. SVID: Subsystem Vendor ID This field will be set to a value corresponding to the PCI Subsystem Vendor ID in the external EEPROM. If there is no EEPROM, this field will default to a value of 10ECh (Realtek Semiconductor’s PCI Subsystem Vendor ID) ...
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... RESERVED (ALL Ptr7 Ptr6 Ptr5 RESERVED (ALL RESERVED (ALL 0) 44 RTL8100C & RTL8100CL Bit4 Bit3 Bit2 Bit1 BMEN MEMEN ...
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... Then the system can be restored to a working state to process incoming jobs. • The RTL8100C(L) can be isolated from the PCI bus automatically via the auxiliary power circuit when the PCI bus state, i.e. the power on the PCI bus is removed. The RTL8100C(L) can be disabled when needed by pulling the isolate pin low to 0V. ...
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... Link Wakeup Link Wakeup occurs when the following conditions are met: • The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8100C( isolation state, or the PME# can be asserted in the current power state. • The Link status is re-established. ...
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... Writing the PME_Status (bit15) of PMCSR register in the PCI Configuration Space will clear this bit and cause the RTL8100C(L) to stop asserting a PME# (if enabled). When the RTL8100C( power down mode, e.g. D1-D3, the IO, and MEM are all disabled. After RST# is asserted, the power state must be changed the original power state was D3 hardware enforced delays in the RTL8100C(L)’ ...
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... Read VPD register (read data from the 93C46) Write the flag bit to a zero at the same time the VPD address is written. When the flag bit is set to one by the RTL8100C(L), the VPD data (all 4 bytes) has been transferred from the 93C46 to the VPD data register. ...
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... The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory. When the entire packet has been transferred to the Tx buffer, the RTL8100C(L) is instructed to move the data from the Tx buffer to the internal transmit FIFO in PCI bus master mode. When the transmit FIFO contains a complete packet or is filled to the programmed threshold level, the RTL8100C(L) begins packet transmission ...
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... After the CRC, the TR symbol pair is inserted. 7.9. Collision If the RTL8100C(L) is not in full-duplex mode, a collision event occurs when the receive input is not idle while the RTL8100C(L) transmits. If the collision was detected during the preamble transmission, a jam pattern is transmitted after completing the preamble (including the JK symbol pair). ...
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... PAUSE packets to achieve flow control tasks. 7.11.1. Control Frame Transmission When the RTL8100C(L) detects that its free receive buffer is less than 3K bytes, it sends a PAUSE packet with pause_time (=FFFFh) to inform the source station to stop transmission for the specified period of time. After the driver has processed the packets in the receive buffer and updated the boundary pointer, the RTL8100C(L) sends another PAUSE packet with pause_time (=0000h) to wake up the source station to restart transmission ...
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... The Link Monitor senses whether a station is connected and monitors link integrity. Note: In 10/100Mbps mode, LED function is the same as that of the RTL8139C(L). 7.12.2. LED_RX Single-Chip Fast Ethernet Controller Power On LED = High No Receiving Packet? Yes LED = High for (100 ±10) ms LED = Low for (12 ±2) ms Figure 3. LED_RX 52 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... LED = High No Transmitting Packet? Yes LED = High for (100 ±10) ms LED = Low for (12 ±2) ms Figure 4. LED_TX Power On LED = High Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( Figure 5. LED_TX+LED_RX 53 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... I OH= -8mA I OL= 8mA V IN GND V OUT GND I OUT= 0mA Conditions I OH= -8mA I OL= 8mA V IN= V dd25 or GND V OUT= V dd2 5 or GND I OUT= 0mA 54 RTL8100C & RTL8100CL Datasheet Units °C +125 °C 70 Minimum Maximum 0.9 * Vcc Vcc 0.1 * Vcc 0.5 * Vcc Vcc+0.5 -0.5 0.3 * Vcc -1 ...
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... AC Characteristics 8.3.1. PCI Bus Operation Timing Target Read Target Write Single-Chip Fast Ethernet Controller Figure 6. Target Read Figure 7. Target Write 55 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Configuration Read Configuration Write Single-Chip Fast Ethernet Controller Figure 8. Configuration Read Figure 9. Configuration Write 56 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Bus Arbitration Memory Read Single-Chip Fast Ethernet Controller Figure 10. Bus Arbitration Figure 11. Memory Read 57 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Memory Write Target Initiated Termination - Retry Single-Chip Fast Ethernet Controller Figure 12. Memory Write Figure 13. Target Initiated Termination - Retry 58 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Target Initiated Termination - Disconnect Figure 14. Target Initiated Termination - Disconnect Target Initiated Termination - Abort Single-Chip Fast Ethernet Controller Figure 15. Target Initiated Termination - Abort 59 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Master Initiated Termination – Abort Parity Operation - One Example Single-Chip Fast Ethernet Controller Figure 16. Master Initiated Termination – Abort Figure 17. Parity Operation - One Example 60 RTL8100C & RTL8100CL Datasheet Track ID: JATR-1076-21 Rev. 1.06 ...
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... Application Information RJ-45 Single-Chip Fast Ethernet Controller EEPROM LED Magnetics RTL8100C(L) PCI INTERFACE Figure 18. Application Information 61 RTL8100C & RTL8100CL Datasheet CLK Auxiliary Power Track ID: JATR-1076-21 Rev. 1.06 ...
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... Mechanical Dimensions 10.1. RTL8100C 128-Pin QFP See the Mechanical Dimensions notes on the next page. Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL 62 Track ID: JATR-1076-21 Rev. 1.06 Datasheet ...
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... Notes for RTL8100C 128-Pin QFP Symbol Dimension in inch Dimension in mm Min Type Max 0.134 A1 0.004 0.010 0.036 A2 0.102 0.112 0.122 0.005 0.009 0.013 b c 0.002 0.006 0.010 D 0.541 0.551 0.561 0.778 0.787 0.797 E e 0.010 0.020 0.030 HD 0.665 0.677 0.689 HE 0.902 0.913 0.925 ...
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... RTL8100CL 128-Pin LQFP See the Mechanical Dimensions notes on the next page. Single-Chip Fast Ethernet Controller RTL8100C & RTL8100CL 64 Track ID: JATR-1076-21 Rev. 1.06 Datasheet ...
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... Notes for RTL8100CL 128-Pin LQFP Symbol Dimension in inch Min Type Max 0.067 A1 0.000 0.004 0.008 0.00 A2 0.051 0.055 0.059 1.30 b 0.006 0.009 0.011 0.15 0.004 - 0.006 0.09 c 0.541 0.551 0.561 13.75 14. 0.778 0.787 0.797 19.75 20. 0.020 BSC HD 0.620 0.630 0.640 15.90 16.00 HE 0.855 0.866 0.877 21.70 22.00 L 0.016 0.024 0.031 0.45 ...