ALC100P REALTEK, ALC100P Datasheet
ALC100P
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ALC100P Summary of contents
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... Avance Logic,Inc. ALC100/ALC100P AC’97 Audio CODEC Revision 1.1 May 25, 2000 ALC100 ...
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Avance Logic,Inc. 1. Features : Single chip audio CODEC with high S/N ratio 16-bit ADC and DAC resolution. l Compliant with AC’97 2.1 specification l Supports AMR and CNR applications. 16-bit stereo full-duplex CODEC with fixed 48k ...
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Avance Logic,Inc. VREFOUT O DALO O DARO O VRADDA O DALI O DALO O ADLO O ADRO O ADLI O ADRI O 2.4 Power/Ground : 8 pins Name Type AVDD1 I AVDD2 I AVSS1 I AVSS2 I VDD1 I ...
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... DVdd2 SYNC RESET# PC_BEEP ALC100/ALC100P Pinout Diagram of ALC100/ALC100P - 4 – ALC100 LINE_OUT_R 36 LINE_OUT_L 35 ADLO 34 33 DARI DALI 32 31 VRADDA 30 DARO DALO 29 Vrefout 28 Vref 27 AVss1 26 25 AVdd1 ...
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Avance Logic,Inc. 4. Mixer Register : All mixer register access with odd-number will return with 0. Reading unimplemented registers will return 0. MX00 Reset Bit Type 15 14: ...
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Avance Logic,Inc. response when read with x11111 too. MX0A PC BEEP Volume Bit Type 15 R/W 14:5 4:1 R/W 0 ΠFor PBV, 00h 0Fh MX0C PHONE Volume Bit Type 15 R/W 14:5 4:0 R/W ΠFor PV, 00h ...
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Avance Logic,Inc. 15 R/W 14:13 12:8 R/W 7:5 4:0 R/W ΠFor VLV/VRV, 00h 08h 1Fh MX16 AUX Volume Bit Type 15 R/W 14:13 12:8 R/W 7:5 4:0 R/W ΠFor ALV/ARV, 00h 08h 1Fh MX18 PCM_OUT Volume Bit ...
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Avance Logic,Inc. MX1C Record Gain Bit Type 15 R/W 14:12 11:8 R/W 7:4 3:0 R/W ΠFor LRG/RRG 0Fh 00h MX20 General Purpose Register Bit Type 15 R R/W 12:10 9 R/W 8 R/W 7 R/W 6:0 ...
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Avance Logic,Inc. ÊID1 is latched inversely from pin 46 when system reset. ID0 is latched inversely from pin 45 when system reset. ËALC100 map DAC slot according to the following table ID[1.. MX72 Extension control ...
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Avance Logic,Inc. 5. Design Suggestion : 5.1 Clocking : The clock source of different configuration is listed below : CODEC ID[1.. 5.2 AC-Link : When ALC100 take serial data from AC97 controller, it sample SDATA_OUT ...
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Avance Logic,Inc. Fig 5.4-1 Example of differential CD input 5.5 Odd Addressed Register Access : ALC100 will not response to odd-addressed register access for future compatibility. 5.6 Power-down Mode : Pay special attention to powerdown control register (index 26h),expecially ...
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Avance Logic,Inc. 6.2.2 Warm Reset : Parameter SYNC active high pulse width SYNC inactive to BIT_CLK Startup delay AC-Link Clocks : 6.2.3 Parameter BIT_CLK frequency BIT_CLK period BIT_CLK output jitter BIT_CLK high pulse width (note 2) T BIT_CLK low ...
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Avance Logic,Inc. Output Valid Delay from rising edge of BIT_CLK Note 1 : Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output. Note 2 : 50pF external load Input Setup to ...
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Avance Logic,Inc. Note 1 : 50pF external load Note 2 : rise is from 10% to 90% of Vdd (V Note 3 : fall is from 90% to 10% of Vdd (V 6.2.6 AC-Link Low Power Mode Timing : ...
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Avance Logic,Inc. 7. Analog Performance Characteristics : Standard test condition : T Full scale input voltage Line inputs Mic inputs Full scale output voltage Line output Analog S LINE_OUT Other to LINE_OUT Analog frequency response Digital S/N ...
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Avance Logic,Inc. 8. Package: SYMBOL MIN 0.05 A2 1. 0.45 MILLIMETER TYP. MAX. 1.60 0.15 1.40 1.45 0.20 9.00 BSC 7.00 BSC 5.50 9.00 ...