AD9816 Analog Devices, AD9816 Datasheet
AD9816
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AD9816 Summary of contents
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... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. PRODUCT DESCRIPTION The AD9816 is a complete analog signal processor for CCD and CIS applications. Included is all the necessary circuitry to perform three-channel conditioning and sampling for a variety of imaging applications ...
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... Input voltage range is the linear region over which the input signal can be processed by the input stage of the AD9816. 3 The input limits are defined as the maximum tolerable input voltage into the AD9816. This is not intended to be the linear input range of the device. Signals beyond the input limits will turn on the overvoltage protection diodes. ...
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... RDV –3– MHz, ADCCLK Typ Max Units Typ Max Units – ADCLK MHz (Fixed) ADCCLK Cycles AD9816 ...
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... AD9816 PIXEL n ( ANALOG INPUTS CDSCLK1 t C1C2 CDSCLK2 t t ADCLK ADC2 ADCCLK t ADCLK OUTPUT DATA R(n–2) G(n–2) B(n–2) D11:D0 PGAOUT_T G(n–1) B(n–1) PGAOUT_C PIXEL n ( ANALOG AD INPUTS CDSCLK2 t t ADC2 ADCLK ADCCLK t ADCLK OUTPUT DATA R(n–2) G(n– ...
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... ADCCLK OUTPUT DATA D11:D0 OEB REV. A PIXEL n PIXEL (n+ CRB t C2AD ADCLK PIXEL (n–3) PIXEL n PIXEL (n+1) Figure 4. 1-Channel SHA Mode Timing EFFECTIVE PIXELS t OD Figure 6. Output Enable Timing –5– PIXEL (n+2) PIXEL (n+m) PIXEL (n–2) PIXEL (n–1) PIXEL (n+ AD9816 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9816 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... CAPT 3 CAPT 4 CAPB 5 AD9816 CAPB 6 TOP VIEW VREF (Not to Scale) 7 CML 8 VINR 9 AVSS 10 VING CONNECT –7– AD9816 DRVSS 32 DB5 DB4 31 30 DB3 29 DB2 28 DB1 27 DB0 (LSB) 26 DVSS SLOAD 25 24 SDATA ...
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... LSBs. APERTURE DELAY The aperture delay is the time delay that occurs from when a sampling edge is applied to the AD9816 until the actual sample of the input signal is held. For CDSCLK1, the aperture delay represents the amount of time it takes for the clamp switch to open after CDSCLK1 transitions from high to low ...
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... The Configuration Register controls the operating mode of the AD9816. Bits 7 (MSB), 6 and 0 are test mode bits and should always be set to zero. Bit 5 is set high to enable the CDS mode. Setting this bit low enables the SHA mode. Set Bit 4 high to enable the 3 V input span ...
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... Channels SERIAL TIMING The 3-wire serial interface timing is shown below. To write to the AD9816, SLOAD is first taken low. Next, a total of 16 bits are sent to SDATA, which get latched into the AD9816 on the rising edges of SCLK. Additional SCLK pulses will be ignored. The first bit, R/W, should be low to specify a write operation. ...
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... An input dc bias level allows a maximum 3 V p-p signal swing from the CCD. Figure 14 shows a typical full-scale input waveform to the AD9816, illustrating the allowable input range. With a reference level the AD9816 can tolerate reset feedthrough above the reference level. The inputs REV the AD9816 can also handle an input signal down to AVSS – ...
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... ADC input signal. PGAOUT_T and PGAOUT_C should only be used during evaluation; perfor- CDSCLK2 mance of the AD9816 is only guaranteed with these two pins unconnected. –12– Gain Code PGA Gain 1 51 ...
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... The AD9816 uses a high speed 12-bit ADC core. This CMOS converter is designed to run at 6 MSPS with good linearity and noise performance. Figure 19 shows the INL and DNL perfor- mance of a typical AD9816 device, running at 6 MHz in 3-channel CDS mode using the timing shown in Figure 1. The following timing parameters were used: t ...
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... GREEN_IN BLUE_IN supply pin should still be decoupled to the same ground plane as the rest of the AD9816. The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC using external digital buffers. All 0.01 F and 0.1 F decoupling capacitors should be located as close as pos- sible to the AD9816 pins. Also, the 1200 pF input capacitors should be located close the AD9816’ ...
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... F 1.0 F RED_IN GREEN_IN BLUE_IN 1.0 F 0.1 F REV. A reference black level of the CIS can be connected to the OFF- SET pin, to remove the dc offset. Removing the coarse offset of the CIS signal will allow the dynamic range of the AD9816 to be maximized 0.01 F AVDD 1 AVSS 2 3 CAPT ...
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... AD9816 0.01 (0.25) MIN OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead MQFP (S-44) 0.529 (13.45) 0.510 (12.95) 0.096 (2.45) 0.398 (10.1) MAX 0.390(9.90) 0.041 (1.03) 0.029 (0.73 SEATING PLANE TOP VIEW (PINS DOWN 0.009 (0.23) 0.005 (0.13) 0.018 (0.45) 0.031 (0.80) 0.083 (2.1) BSC 0.012 (0.30) 0.077 (1.95) –16– 0.333 (8.45) 0.327 (8. REV. A ...