RTL8100B REALTEK, RTL8100B Datasheet
RTL8100B
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RTL8100B Summary of contents
Page 1
... RX_ER Counter ................................................. 29 5.27 CS Configuration Register ................................. 30 5.28 Config5: Configuration Register 5 ..................... 31 2001-11-9 RTL8100B(L) 6. EEPROM (93C46) Contents .....................................32 6.1 Summary of the RTL8100B(L) EEPROM Registers...34 6.2 Summary of EEPROM Power Management Registers .34 7. PCI Configuration Space Registers..........................35 7.1 PCI Configuration Space Table ............................35 7.2 PCI Configuration Space Functions......................37 7.3 Default Values after Power-on (RSTB asserted) ..40 7 ...
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... Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse) Supports auxiliary power-on internal reset ready Note: The model number of the QFP package is RTL8100B. The LQFP package model number is RTL8100BL. 2001-11-9 for remote wake-up when main power still remains off ...
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... RTL8100B(L) LAN card). The information may consist of part number, serial number, and other detailed information. To provide cost down support, the RTL8100B(L) is capable of using a 25MHz crystal or OSC as its internal clock source. The RTL8100B(L) keeps network maintenance costs low and eliminates usage barriers the easiest way to upgrade a network from 10 to 100Mbps. It also supports full-duplex operation, making 200Mbps bandwidth possible at no additional cost. To improve compatibility with other brands’ ...
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... VDD 98 CBE3B 99 IDSEL 100 AD23 1 AD22 2 GND 3 AD21 4 AD20 5 AD19 6 VDD AD18 9 AD17 10 AD16 11 CBE2B 12 FRAMEB 13 IRDYB 14 TRDYB 15 DEVSELB 2001-11-9 RTL8100B QFP 4 RTL8100B(L) 65 RTSET 64 LWAKE 63 RTT3 62 GND AVDD 58 AVDD25 57 PMEB 56 GND 55 VCTRL VDD25 50 AUX 49 EECS ...
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... RXIN AVDD 71 TXD- 72 TXD+ 73 GND 74 ISOLATEB 75 AVDD LED2 LED1 80 LED0 81 INTAB 82 RSTB 83 CLK 84 GNTB 85 REQB 86 AD31 RTL8100BL LQFP 87 AD30 88 GND 89 AD29 90 VDD 91 AD28 92 AD27 93 AD26 94 AD25 95 AD24 96 VDD25 97 VDD 98 CBE3B 99 IDSEL 100 AD23 1 AD22 2 GND 3 AD21 4 AD20 5 AD19 ...
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... Device Select bus master, the RTL8100B (L) samples this signal to insure that a PCI target recognizes the destination address for the data transfer target, the RTL8100B(L) asserts this signal low when it recognizes its target address after FRAMEB is asserted. 12 Cycle Frame bus master, this pin indicates the beginning and duration of an access ...
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... Grant: This signal is asserted low to indicate to the RTL8100B(L) that the central arbiter has granted ownership of the bus to the RTL8100B (L). This input is used when the RTL8100B(L) is acting as a bus master. 85 Request: The RTL8100B(L) will assert this signal low to request the ownership of the bus from the central arbiter. ...
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... Pin No 50 Aux. Power Detect: This pin is used to notify the RTL8100B(L) of the existence of Aux. power during initial power- PCI reset. This pin should be pulled high to the Aux. power via a resistor to detect the Aux. power. Doing so, will enable wakeup support from ACPI D3 cold or APM power-down ...
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... It must be left open when X1 is driven with an external 25 MHz oscillator. Pin No 63 Chip test pin 65 This pin must be pulled low by a resistor. Please refer to the application circuit for the correct value. 55 Use this pin and an external PNP type transistor to generate +2.5V for the RTL8100B(L). Reserved 54, 69, 76 RTL8100B(L) Description Description Rev.1.41 ...
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... Register Descriptions The RTL8100B(L) provides the following set of operational registers mapped into PCI memory space or I/O space. Offset R/W 0000h R/W 0001h R/W 0002h R/W 0003h R/W 0004h R/W 0005h R/W 0006h-0007h - 0008h R/W 0009h R/W 000Ah R/W 000Bh R/W 000Ch R/W 000Dh R/W 000Eh R/W 000Fh R/W 0010h-0013h R/W 0014h-0017h R/W 0018h-001Bh R/W 001Ch-001Fh R/W 0020h-0023h R/W 0024h-0027h R/W 0028h-002Bh R/W 002Ch-002Fh R/W 0030h-0033h ...
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... LSB of the mask byte of wakeup frame2 within offset LSBCRC3 LSB of the mask byte of wakeup frame3 within offset LSBCRC4 LSB of the mask byte of wakeup frame4 within offset LSBCRC5 LSB of the mask byte of wakeup frame5 within offset RTL8100B(L) Rev.1.41 ...
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... CRC CRC Error: When set, indicates that a CRC error occurred on the received packet. FAE Frame Alignment Error: When set, indicates that a frame alignment error occurred on this received packet. ROK Receive OK: When set, indicates that a good packet is received. 12 RTL8100B(L) Description Rev.1.41 ...
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... Transmit Status Register (TSD0-3)(Offset 0010h-001Fh, R/W) The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8100B(L) when the Transmit Byte Count (bits 12-0) in the corresponding Tx descriptor is written not affected when software writes to these bits. These registers are only permitted to write by double-word access. After a software reset, all bits except OWN bit are reset to “0”. ...
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... R 5.4 Command Register (Offset 0037h, R/W) This register is used for issuing commands to the RTL8100B(L). These commands are issued by setting the corresponding bits for the function. A global software reset along with individual reset and enable/disable for transmitter and receiver are provided here. Bit R/W ...
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... Receive Error Interrupt: 1 => Enable, 0 => Disable. ROK Receive OK Interrupt: 1 => Enable, 0 => Disable. Symbol SERR System Error: Set to 1 when the RTL8100B(L) signals a system error on the PCI bus. TimeOut Time Out: Set to 1 when the TCTR register reaches to the value of the TimerInt register. ...
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... Transmit Configuration Register (Offset 0040h-0043h, R/W) This register defines the Transmit Configuration for the RTL8100B(L). It controls such functions as Loopback, programmable Interframe Gap, Fill and Drain Thresholds, and maximum DMA burst size. Bit R 30-26 R 25-24 R/W 23-22 R 21-19 - 18, 17 R/W 16 R/W 15-11 - 10-8 R/W 2001-11-9 Symbol - Reserved HWVERID_A Hardware Version ID A: ...
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... R/W 3 5.8 Receive Configuration Register (Offset 0044h-0047h, R/W) This register is used to set the receive configuration for the RTL8100B(L). Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. are controlled here. Bit R/W 31-28 - 27-24 R/W 23- R/W 16 R/W 2001-11-9 TXRR Tx Retry Count: These are used to specify additional transmission retries in multiple of 16 (IEEE 802 ...
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... Unlimited WRAP When set to 0: The RTL8100B(L) will transfer the rest of the packet data into the beginning of the Rx buffer if this packet has not been completely moved into the Rx buffer and the transfer has arrived at the end of the Rx buffer. ...
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... Command Register (Offset 0050h, R/W) This register is used for issuing commands to the RTL8100B(L). These commands are issued by setting the corresponding bits for the function. A warm software reset along with individual reset and enable/disable for transmitter and receiver are provided as well. ...
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... Writing Writing When the command register bits IOEN, MEMEN, and BMEN of the PCI configuration space are written, the RTL8100B(L) will clear this bit automatically. LWAKE active mode: The LWACT bit and LWPTN bit in CONFIG4 register are used to program the LWAKE pin’s output signal. According to the combination of these two bits, there may be 4 choices of LWAKE signal, i ...
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... Inverse of Link status Link OK Link Fail. TXPF Set, when RTL8100B(L) sends pause packet. Reset, when RTL8100B(L) sends timer done packet. RXPF Pause Flag: Set, when RTL8100B( backoff state because a pause packet received. Reset, when pause state is clear. 21 RTL8100B(L) Description ...
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... Link 100Mbps mode. Magic Magic Packet: This bit is valid when the PWEn bit of the CONFIG1 register is set. The RTL8100B(L) will assert the PMEB signal to wakeup the operating system when the Magic Packet is received. Once the RTL8100B(L) has been enabled for Magic Packet wakeup ...
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... Set to 0: The RTL8100B(L) supports wake-up frames, each with masked bytes selected from offset 12 to 75. Set to 1: The RTL8100B(L) supports wake-up frames, each with 16-bit CRC algorithm for MS Wakeup Frame, the low byte of 16-bit CRC should be placed at the correspondent CRC register, and the high byte of 16-bit CRC should be placed at the correspondent LSBCRC register ...
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... Multiple Interrupt Select Register (Offset 005Ch-005Dh, R/W) If the received packet data is not a familiar protocol (IPX, IP, NDIS, etc.) to the RTL8100B(L), RCR<ERTH[3:0]> will not be used to transfer data in early mode. This register will be written to the received data length in order to make an early Rx interrupt for the unfamiliar protocol. ...
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... This bit allows the NWay auto-negotiation function to be reset re-start auto-negotiation normal operation. This bit sets the duplex mode full-duplex normal operation. This bit‘s initial value comes from 93C46. If bit12 = 1, read = status write = register value. If bit12 = 0, read = write = register value. Reserved 25 RTL8100B(L) Description Default/Attribute ...
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... Link had been experienced fail state 1 = valid link established valid link established jabber condition detected jabber condition detected extended register capability basic register capability only. 26 RTL8100B(L) Default/Attribute ...
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... Binary encoded selector supported by this node. Currently only CSMA/CD <00001> is specified. No other protocols are supported. 27 RTL8100B(L) Default/Attribute The default value ...
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... This bit indicates if the local node is able to send additional Next Pages. This bit is set when a new Link Code Word Page has been received. The bit is automatically cleared when the auto-negotiation link partner’s ability register (register 5) is read by management link partner supports NWay auto-negotiation. 28 RTL8100B(L) Default/Attribute ...
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... LED0 Pin indicates linkpulse 1 = Auto-neg experienced ability detect state 1 = Auto-neg experienced parallel detection fault state 1 = Auto-neg experienced link status check state Description/Usage This 16-bit counter increments by 1 for each valid packet received cleared to zero by a read command. 29 RTL8100B(L) Default/Attribute h'[0000], R Default/Attribute h'[0000], R Default/Attribute ...
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... Assertion of this bit forces the disconnect function to be bypassed. Reserved This bit indicates the status of the connection valid connected link detected disconnected link detected. Assertion of this bit configures LED1 pin to indicate connection status. Reserved Bypass Scramble 30 RTL8100B(L) Default/Attribute 0, ...
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... R/W 1 R/W 0 R/W Config5 register, offset D8h: (SYM_ERR register is changed to Config5, the function of SYM_ERR register is no longer supported by RTL8100B(L).) The 3 bits (bit2-0) are auto-loaded from EEPROM Config5 byte to RTL8100B(L) Config5 register. 2001-11-9 Symbol - Reserved BWF Broadcast Wakeup Frame: 1: Enable Broadcast Wakeup Frame with mask bytes of only DID field = ...
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... The 93C46 is a 1K-bit EEPROM. Although it is actually addressed by words, its contents are listed below by bytes for convenience. The RTL8100B(L) performs a series of EEPROM read operations from the 93C46 addresses 00H to 31H suggested to obtain Realtek approval before changing the default settings of the EEPROM. ...
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... PHY Parameter 1-T for RTL8100B(L). Operational registers of the RTL8100B(L) are from 78h to 7Bh. Reserved. Do not change this field without Realtek approval. PHY Parameter 2-T for RTL8100B(L). Operational register of the RTL8100B(L) is 80h. Reserved. Reserved. Do not change this field without Realtek approval. Checksum of the EEPROM content. ...
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... Summary of the RTL8100B(L) EEPROM Registers Offset Name Type * 00h-05h IDR0 – IDR5 R/W 51h CONFIG0 52h CONFIG1 58h MSRBMCR 63H 59h CONFIG3 5Ah CONFIG4 R/W RxFIFOA ** 78h-7Bh PHY1_PARM R/W ** 7Ch-7Fh TW1_PARM R/W TW2_PARM ** 80h PHY2_PARM R/W * D8h CONFIG5 R/W The registers marked with type = ' can be written only if bits EEM1=EEM0=1. ...
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... SVID11 SVID10 SMID4 SMID3 SMID2 SMID12 SMID11 SMID10 - - - ILR4 ILR3 ILR2 RTL8100B(L) Bit1 Bit0 MEMEN IOEN MEMEN IOEN FBTBEN SERREN - SERREN 0 0 DST0 DPD - DPD ...
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... VPDADD VPDADD VPDADD VPDADD VPDADD VPDADD R12 R11 R10 Data4 Data3 Data2 Data12 Data11 Data10 Data20 Data19 Data18 Data28 Data27 Data26 RTL8100B(L) D1 Aux_I_b2 Power State Power State - PME_En - PME_En VPDADD R1 R0 VPDADD R9 R8 Data1 Data0 Data9 Data8 Data17 ...
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... Special Cycle Enable: Read as 0, write operation has no effect. The RTL8100B(L) ignores all special cycle operation. 2 BMEN Bus Master Enable: When set to 1, the RTL8100B(L) is capable of acting as a bus master. When set prohibited from acting as a PCI bus master. For the normal operation, this bit must be set by the system BIOS. 1 MEMEN Memory Space Access: When set to 1, the RTL8100B(L) responds to memory space accesses ...
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... Because the PCI version 2.1 specification does not define any specific value for network devices, PIFR = 00h. SCR: Sub-Class Register The Sub-class register is an 8-bit register that identifies the function of the RTL8100B(L). SCR = 00h indicates that the RTL8100B( Ethernet controller. ...
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... INTA interrupt pin. Read only. IPR = 01H. MNGNT: Minimum Grant Timer: Read only Specifies how long a burst period the RTL8100B(L) needs at 33 MHz clock rate in units of 1/4 microsecond. This field will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h. ...
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... RESERVED (ALL Ptr7 Ptr6 Ptr5 RESERVED (ALL RESERVED (ALL 0) 40 RTL8100B(L) Bit4 Bit3 Bit2 BMEN MEMEN NewCap RTABT STABT ...
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... PMC 76 not recommended to set the D0_support_PME bit to “1”. Link Wakeup occurs only when the following conditions are met: ♦ The LinkUp bit (CONFIG3#4) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8100B( isolation state, or the PME# can be asserted in current power state. ♦ ...
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... When the RTL8100B( power down mode, ex. D1-D3, the IO, and MEM are all disabled. After RST# asserted, the power state must be changed the original power state is D3 state. When in ACPI mode, the RTL8100B(L) does not support PME from D0 (owing to the setting of PMC register. This setting comes from EEPROM). ...
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... Read VPD register: (read data from 93C46) Write the flag bit to a zero at the same time the VPD address is written. When the flag bit is set to one by the RTL8100B(L), the VPD data (all 4 bytes) has been transferred from 93C46 to the VPD data register. ...
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... Voltage 44 LED Driver Transmit/ Receive Logic Interface Interface RXD Descrambler RXC 25M TXD TXC 25M Link pulse 10M Output waveform shaping Receive low pass filter 3 Level Driver Peak Detect Adaptive Equalizer Master PPL 25M RTL8100B(L) MII TXO+ TXO - RXIN+ RXIN- Rev.1.41 ...
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... The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory. When the entire packet has been transferred to the Tx buffer, the RTL8100B(L) is instructed to move the data from the Tx buffer to the internal transmit FIFO in PCI bus master mode. When the transmit FIFO contains a complete packet or is filled to the programmed threshold level, the RTL8100B(L) begins packet transmission ...
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... After detecting receive activity on the line, the RTL8100B(L) starts to process the preamble bytes based on the mode of operation. While operating in 100Base-Tx mode, the RTL8100B(L) expects the frame to start with the symbol pair JK in the first bye of the 8-byte preamble. The RTL8100B(L) checks the CRC bytes and checks if the packet data ends with the TR symbol pair, if not, the RTL8100B(L) reports an CRC error RSR. The RTL8100B(L) reports a RSR< ...
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... In 10/100 Mbps mode, the LED function is like the RTL8139C(L). 9.12.3 LED_TX 2001-11-9 Power On LED = Low No Receiving Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( Power On LED = Low No Transmitting Packet Yes LED = High for (100 +- 10) ms LED = Low for ( RTL8100B(L) Rev.1.41 ...
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... LED_TX+LED_RX 10. Application Diagram RJ45 Magetics 2001-11-9 Power On LED = Low Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( EEPROM LED CLK RTL8100B(L) Auxiliary Power PCI INTERFACE 48 RTL8100B(L) No Rev.1.41 ...
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... V IN -1.0 GND V OUT -10 GND I OUT= 0mA, Conditions Minimum I OH= -8mA 0.9 * Vdd25 I OL= 8mA 0.5 * Vdd25 -0.5 V IN= V dd25 or -1.0 GND V OUT= V dd25 or -10 GND I OUT= 0mA, 49 RTL8100B(L) Units °C °C Maximum Units Vcc V 0.1 * Vcc V Vcc+0.5 V 0.3 * Vcc V 1 330 mA Maximum Units ...
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... AC Characteristics 11.3.1 PCI Bus Operation Timing Target Read Target Write 2001-11-9 50 RTL8100B(L) Rev.1.41 ...
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... Configuration Read Configuration Write 2001-11-9 51 RTL8100B(L) Rev.1.41 ...
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... BUS Arbitration Memory Read 2001-11-9 52 RTL8100B(L) Rev.1.41 ...
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... Memory Write Target Initiated Termination - Retry 2001-11-9 53 RTL8100B(L) Rev.1.41 ...
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... Target Initiated Termination - Disconnect Target Initiated Termination - Abort 2001-11-9 54 RTL8100B(L) Rev.1.41 ...
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... Master Initiated Termination – Abort Parity Operation - one example 2001-11-9 55 RTL8100B(L) Rev.1.41 ...
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... Millimeter 0.11 0.51 0.91 4.General appearance spec. should be based on final visual 2.60 3.10 inspection spec. 2.85 0.18 0.30 0.42 0.04 0.15 0.26 TITLE : 100L QFP ( 14x20 mm**2 ) FOOTPRINT 4.8 mm 0.50 0.65 0.80 APPROVE 1.00 1.20 1.40 2.25 2.40 2.65 CHECK - - 0.10 0° - 12° 56 PACKAGE OUTLINE DRAWING LEADFRAME MATERIAL: DWG NO. REV NO. SCALE Ricardo Chen DATE SHT NO. REALTEK SEMICONDUCTOR CORP. RTL8100B( Rev.1.41 ...
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... BSC 0.40 0.60 0.80 APPROVE 1.00 REF 0° 3.5° 9° 0° CHECK 12°TYP 12°TYP 57 and E do not include mold protrusion are maximum plastic body size dimensions TITLE : 100LD LQFP ( 14x14x1.4mm) LEADFRAME MATERIAL: DOC. NO. VERSION PAGE DWG NO. LQ100 - P1 DATE REALTEK SEMICONDUCTOR CORP. RTL8100B( Rev.1.41 ...
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... Realtek Semiconductor Corp. Headquarters No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw 2001-11-9 58 RTL8100B(L) Rev.1.41 ...