AD7760BSV Analog Devices, AD7760BSV Datasheet
AD7760BSV
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AD7760BSV Summary of contents
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... Rev. PrN Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...
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AD7760 TABLE OF CONTENTS TABLE OF CONTENTS.................................................................. 2 AD7760—Specifications.................................................................. 3 Timing Specifications....................................................................... 5 Timing Diagrams.............................................................................. 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Functional Descriptions.......................... 8 Terminology .................................................................................... 10 Typical Performance Characteristics ........................................... 11 Theory of Operation ...
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Preliminary Technical Data AD7760—SPECIFICATIONS Table 2 4.096 V, T DD1 DD2 REF Parameter DYNAMIC PERFORMANCE Decimate by 256 1 Signal to Noise Ratio (SNR) Spurious Free Dynamic Range (SFDR) 1 ...
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AD7760 Parameter Full Power Mode AI (Modulator) DD1 AI (General) DD2 AI (Reference Buffer) DD4 Low Power Mode AI (Modulator) DD1 AI (General) DD2 AI (Reference Buffer) DD4 AI (Diff Amp) DD3 D IDD Standby Mode AI (Modulator) DD1 AI ...
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Preliminary Technical Data TIMING SPECIFICATIONS Table 2 4.096 V, V DD1 DD2 REF Parameter Limit MIN MAX f 12.288 MCLK 80 f 12.288 ICLK 20 1 ...
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AD7760 TIMING DIAGRAMS Figure 2. Parallel Interface Timing Diagram Figure 3. 20MHz Modulator Data Output Mode Figure 4. AD7760 Register Write Rev. PrN | Page Preliminary Technical Data ...
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Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 25°C, unless otherwise noted. A Parameters V to GND GND IN GND IN– Digital input voltage to GND Digital output voltage to GND V to ...
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AD7760 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS DGND 1 PIN 1 MCLK 2 IDENTIFIER MCLK 3 AV DD2 4 AGND 5 AV DD1 6 AGND ...
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Preliminary Technical Data TQFP Pin CSP Pin Pin Mnemonic Number Number A1 A1 A1- OUT A1+ OUT ...
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AD7760 TERMINOLOGY Signal to (Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals ...
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Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS Default Conditions 25°C, TBD, unless otherwise noted. A Figure 7. TBD Figure 8. TBD Figure 9. TBD Rev. PrN | Page AD7760 Figure 10. TBD Figure 11. TBD Figure ...
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AD7760 THEORY OF OPERATION The AD7760 employs a sigma-delta conversion technique to convert the analog input into an equivalent digital word. The modulator samples the input waveform and outputs an equivalent digital word to the digital filter at a rate ...
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Preliminary Technical Data AD7760 INTERFACE Reading Data The AD7760 uses a 16-bit bi-directional parallel interface. This interface is controlled by the RD /WR and CS pins. There are two read operating modes depending on the output data rate. When the ...
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AD7760 CLOCKING THE AD7760 The AD7760 requires an external low jitter clock source. This signal is applied to the MCLK and MCLK pins. An internal clock signal (ICLK) is derived from the MCLK input signal. This ICLK controls all the ...
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Preliminary Technical Data DRIVING THE AD7760 The AD7760 has an on-chip differential amplifier. This amplifier will operate with a supply voltage (AV 5.5V. For a 4.096V reference, the supply voltage must be 5V. To achieve the specified performance in full ...
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AD7760 USING THE AD7760 The following is the recommended sequence for powering up and using the AD7760. 1. Apply Power 2. Start clock oscillator, applying MCLK Take RESET low for a minimum of 1 MCLK cycle 3. Wait a minimum ...
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Preliminary Technical Data PROGRAMMABLE FIR FILTER As previously mentioned, the third FIR filter on the AD7760 is user programmable. The default coefficients that are loaded on reset are given in Table 8. This gives a frequency response shown in Figure ...
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AD7760 DOWNLOADING A USER-DEFINED FILTER As previously mentioned, the filter coefficients are 27 bits in length; one sign and 26 magnitude bits. Since the AD7760 has a 16-bit parallel bus, the coefficients are padded with 5 MSB zeros to generate ...
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Preliminary Technical Data Table 11 shows the Hex values (in sign and magnitude format) that are downloaded to the AD7760 to realize this filter. The table is also split into the bytes which are all summed to produce the checksum. ...
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AD7760 AD7760 REGISTERS The AD7760 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter configuration, the clock divider etc. There are also digital gain, offset and over-range threshold registers. Writing to ...
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Preliminary Technical Data Table 14. Status Register (Read Only) MSB PART PART DIE DIE DIE DVALID Bit Mnemonic Comment 15,14 PART1:0 Part Number. These bits will be constant for the AD7760. 13-11 DIE2:0 Die Number. ...
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... Figure 22. 64-Lead Thin Quad Flat Pack (Exposed Paddle) [TQFP] (SV-64)—Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range AD7760BCP –40°C to +85°C AD7760BSV –40°C to +85°C © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Printed in the U.S.A. PR04975-0-6/04(PrN) ...