LP62S1024AX-70LLT/ REALTEK, LP62S1024AX-70LLT/ Datasheet
LP62S1024AX-70LLT/
Related parts for LP62S1024AX-70LLT/
LP62S1024AX-70LLT/ Summary of contents
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... Further power reduction can be done via a 1.25:1 transformer on the transmit side with power down to 1.28 W(max.). For ease of system design, only one external clock source is needed when operating with Realtek 8-port switch controller, RTL8308, to produce a high performance switch system. Additionally, optimized pinouts are taken such that direct routing can be implemented, which simplifies the layout work and also gain EMI noise reduction ...
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Document Revision Information Revision Date 1.00 04/20/2000 Original document. 1.01 05/08/2000 First SMI read/write cycle after power-on reset. P.7 and P.15.. 1.02 05/12/2000 Power-on VCC rising time to complete auto-reset. P.6. Reset description in details. P.12. 1.03 05/29/2000 Add 100Base-FX ...
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Block Diagram RXCLK RXD[3:0] RXD[1:0] CRSDV CRS RXDV COL TXCLK TXEN TXEN TXER TXD[3:0] TXD[1:0] 4. Pin Assignments 4B/5B DECODE RX STATE MACHINE BYP-DESCR 100BASE-TX RECEIVER 100BASE-TX TRANSMITTER TX STATE MACHINE BYP-SCR 3 FXRP/N SDP/N (PORT[D] ONLY) RXIP/N 10/100 ...
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REFCLK 67 DVDD 68 RXD[1][B] 69 RXD[0][B] 70 RXER[B] 71 CRSDV[B] 72 DGND 73 DGND 74 TXD[1][B] 75 TXD[0][B] 76 TXE[B] 77 DVDD 78 RXD[1][A] 79 RXD[0][A] 80 DVDD 81 RXER[A] 82 CRSDV[A] 83 DGND 84 TXD[1][A] 85 TXD[0][A] ...
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AGND, 4, TXOP[A], 5, TXON[A], 6, AVDD, 7, AVDD, 8, TXON[B], 9, TXOP[B], 10, AGND, 11, AGND, 12, RXIP[B], 13, RXIN[B], 14, AVDD, 15, AVDD, 16, RXIN[C]. 17, RXIP[C], 18, AGND, 19, AGND, 20, TXOP[C], 21, TXON[C], 22, AVDD, 23, ...
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PIN NAME Pin RXIP[A], RXIN[A] 2,1 RXIP[B], RXIN[B] 13,14 RXIP[C], RXIN[C] 18,17 RXIP[D], RXIN[D] 29,30 TXOP[A], TXON[A] 5,6 TXOP[B], TXON[B] 10,9 TXOP[C], TXON[C] 21,22 TXOP[D], TXON[D] 26,25 FXRP[D],FXRN[D], 34,35 FXTP[D],FXTN[D] 36,37 SDP[D],SDN[D] 32,33 Power and Ground Pins PIN NAME Pin ...
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RXD[1:0][C] 55,56 RXD[1:0][D] 45,46 CRSDV[A:D] 82,71, 58,48 RXER[A:D] 81,70, 57,47 SMI(Serial Management Interface) pins PIN NAME Pin MDIO 64 MDC 65 LED pins ( LEDs activate as active high or low depending on mode pins. Refer to LED configuration section) ...
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... Reserved pins PIN NAME Pin Reserved 94 6. Registers Description The first six registers of the MII registers are defined by the MII specification. Other registers are defined by Realtek Semiconductor Corp. for internal use and reserved for specific use. Register 0 Control Register 1 Status Register ...
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Auto Negotiation 1 = Enable auto-negotiation process. Enable 0 = disable auto-negotiation process. This bit can be set by ANEG (pin39) or SMI.(Read/Write) For port[D], when 100FX mode is enabled by pulling FX_DIS (pin91) low, this bit =0 regardless ...
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The jabber function is disabled in the 100Base-X. Jabber occurs when a predefined excessive long packet is detected for 10Base-T. When the duration of TXEN exceeds the jabber timer (60ms), the transmit and loopback functions will be disabled and COL ...
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Link Partner. 0=100Base-T4 not supported by Link Partner. 5.8 100Base-TX-FD 1=100Base-TX full duplex supported by Link Partner. 0=100Base-TX full duplex not supported by Link Partner. For port[D] 100FX mode, this bit is set when Reg.0.8=1. ...
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Link Monitor The 10Base-T link pulse detection circuit always monitors the RXIP/RXIN pins for the presence of valid link pulses. Auto-polarity is implemented for correcting the detected reverse polarity of RXIP/RXIN signal pairs. 7.2.4 Jabber Jabber occurs when TXEN ...
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Scrambler/de-scrambler is bypassed in 100Base-FX. 7.4.3 Far-End-Fault-Indication (FEFI) MII Reg.1.4 (Remote Fault) is FEFI bit for port[D] when 100FX enabled, which indicates FEFI has been detected. FEFI is an alternative in-band signaling which is composed of 84 consecutive ...
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Additional power reduction can be gained by a 1.25:1 transformer on its TX side and using a 2.45K pin. External pull-high resistors for TXOP/TXON should be changed from 50 more details. About 20% power is reduced for maximum power consumption. ...
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Application information 8.1 10Base-T/100Base-TX Application RXIP RXIN RTL8204 TXOP TXON FX_DIS IBREF Transformer 1:1 0.1uF 3.3V 0.1uF 1:1 3.3V 3.3V 0.1uF 15 RJ45 0.1uF/3KV Chasis GND ...
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Reduction Application) RXIP RXIN RTL8204 TXOP TXON FX_DIS IBREF Transformer 1:1 0.1uF 3.3V 0.1uF 1.25:1 3.3V 3.3V 0.1uF 16 RJ45 0.1uF/3KV Chasis GND ...
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Application FXRP FXRN RTL8204 SDP SDN FXTN FXTP FX_DIS * The fiber transceiver must work on 3.3V power supply such that it won’t destroy RTL8204 while connecting together. 3.3V VCC_TX (3.3V) 17 VCC_RX (3.3V) Fiber Transceiver 1 GND_RX ...
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Electrical Characteristics 9.1 Absolute Maximum Ratings: WARNING: Absolute maximum ratings are limits beyond which may cause permanent damage to the device or affect device reliability. All voltages are specified reference to GND unless otherwise specified. Parameter Storage Temperature Vcc ...
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TX+/- Output Current High I OH TX+/- Output Current Low I OL RX+/- Common-mode input voltage RX+/- Differential input resistance Differential Input Resistance Input Squelch Threshold 9.4 AC Characteristics(0 C<Ta<70 C, 3.15V<Vcc<3.45V) Parameter SYM Differential Output Voltage peak-to-peak ...
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CRS_DV assert First bit of “T on MDI input to CRS_DV de-assert RX Propagation Delay t RXpd TX Propagation Delay t TXpd TXEN to MDI output Carrier Sense Turn-on t CSON delay Carrier Sense Turn-off t CSOFF Delay RX ...
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Pin PQFP dimension Note: Symbol Dimension (mm) A 3.3 00(max) A 0.100(min 2.85 0.127 2 b 0.26(min) 0.36(max) c 0.150 0.008 D 14.000 0.100 E 20.000 0.100 e 0.650 0.150 H 17.200 0.250 D H 23.200 ...