GS8160E18BGT-200 GSI Technology, GS8160E18BGT-200 Datasheet

GS8160E18BGT-200

Manufacturer Part Number

GS8160E18BGT-200

Description

Manufacturer

GSI Technology

Datasheet

1.GS8160E18BGT-200.pdf (23 pages)

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline opera-

• Dual Cycle Deselect (DCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS8160E18/32/36BT is an 18,874,368-bit (16,777,216-bit

for x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

Rev: 1.03 9/2005

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

tion

Flow Through

Pipeline

3-1-1-1

2-1-1-1

1M x 18, 512K x 32, 512K x 36

18Mb Sync Burst SRAMs

Curr

tCycle

Parameter Synopsis

(x32/x36)

(x18)

1/23

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

DCD Pipelined Reads

The GS8160E18/32/36BT is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. SCD (Single Cycle Deselect)

versions are also available. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of

clock.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS8160E18/32/36BT operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

from the internal circuits and are 3.3 V and 2.5 V compatible.

-250

295

345

225

255

2.5

4.0

5.5

-200

245

285

200

220

3.0

5.0

6.5

DDQ

GS8160E18/32/36BT-250/200/150

) pins are used to decouple output noise

-150

200

225

185

205

3.8

6.7

7.5

Unit

250 MHz–150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS8160E18BGT-200

GS8160E18BGT-200 Summary of contents

Page 1

... KQ 5.5 tCycle 225 Curr (x18) 255 Curr (x32/x36) 1/23 GS8160E18/32/36BT-250/200/150 250 MHz–150 MHz 3.3 V I/O ) pins are used to decouple output noise DDQ -200 -150 Unit 3.0 3.8 ns 5.0 6.7 ns 245 200 mA 285 225 mA 6.5 7.5 ns 6.5 7.5 ns 200 185 mA 220 205 mA © 2004, GSI Technology DD ...

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... Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply 5/23 © 2004, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8160E18/32/36B Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 6/23 GS8160E18/32/36BT-250/200/150 A Memory Array DQx1–DQx9 © 2004, GSI Technology ...

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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write CR CW 9/23 GS8160E18/32/36BT-250/200/150 First Read Burst Read BW, and GW © 2004, GSI Technology ...

Page 10

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram with G X Deselect First Write Burst Write 10/23 GS8160E18/32/36BT-250/200/150 First Read Burst Read CR © 2004, GSI Technology ...

Page 11

... DDQ2 +1.5 V maximum, with a pulse width not to exceed 50% tKC. DDn 11/23 GS8160E18/32/36BT-250/200/150 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 DDQ –0 +0.5 DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2004, GSI Technology Unit Notes ...

Page 12

... Typ – +1.5 V maximum, with a pulse width not to exceed 50% tKC. DDn 12/23 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2004, GSI Technology ...

Page 13

... Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 13/23 GS8160E18/32/36BT-250/200/150 50% tKC DD IL Typ. Max. Unit 30pF © 2004, GSI Technology ...

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... GSI Technology –40 Unit to 85°C 215 mA 20 200 mA 15 195 mA 15 185 ...

Page 16

... GSI Technology ...

Page 17

... Pipeline Mode Timing (DCD) Deselect Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont tKL tKL tKH tKH tKC tKC ADSC initiated read and E3 only sampled with ADSC tS tKQ tOHZ tH tLZ Q(A) D(B) 17/23 GS8160E18/32/36BT-250/200/150 Deselect Deselect Deselected with E1 tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2004, GSI Technology tKQX ...

Page 18

... Flow Through Mode Timing (DCD) Deselect Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read masks ADSP E1 masks ADSP tH tS tOHZ tLZ Q(A) D(B) Q(C) 18/23 GS8160E18/32/36BT-250/200/150 Deselect tH Deselected with E1 tKQX tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2004, GSI Technology ...

Page 19

... Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing tKH tKH tKC tKC tKL tKL tZZS tZZH 19/23 GS8160E18/32/36BT-250/200/150 2. The duration of SB tZZR © 2004, GSI Technology ...

Page 20

... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 20/23 GS8160E18/32/36BT-250/200/150 E1 E © 2004, GSI Technology ...

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... GS8160E36BGT-150 GS8160E18BGT-250I GS8160E18BGT-200I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160E18B-150IT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user ...

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... Ordering Information for GSI Synchronous Burst RAMs (Continued) 1 Org Part Number GS8160E18BGT-150I 512K x 32 GS8160E32BGT-250I 512K x 32 GS8160E32BGT-200I 512K x 32 GS8160E32BGT-150I 512K x 36 GS8160E36BGT-250I 512K x 36 GS8160E36BGT-200I 512K x 36 GS8160E36BGT-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160E18B-150IT. ...

Page 23

... Creation of new datasheet • Updated overshoot/undershoot information Content • Added 300 MHz speed bin Content • Removed 300 MHz speed bin Content • Added Status column to Ordering Information table • Changed Pb-free to RoHS-compliant 23/23 GS8160E18/32/36BT-250/200/150 Page;Revisions;Reason © 2004, GSI Technology ...

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