GS82032AT-6 GSI Technology, GS82032AT-6 Datasheet

GS82032AT-6

Manufacturer Part Number

GS82032AT-6

Description

100MHz 12ns 64K x 32 2M synchronous burst SRAM

Manufacturer

GSI Technology

Datasheet

1.GS82032AT-5.pdf (23 pages)

Current page: 1 of 23
Download datasheet (678Kb)

TQFP, QFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipelined

• Single Cycle Deselect (SCD) operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP or QFP package

Functional Description

Applications

The GS82032A is a 2,097,152-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Rev: 1.09 7/2002

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Through

operation

Pipeline

3-1-1-1

2-1-1-1

Flow

tCycle

155 mA

100 mA

5.5 ns

3.2 ns

9.1 ns

-180

8 ns

2M Synchronous Burst SRAM

140 mA

90 mA

3.5 ns

8.5 ns

10 ns

-166

6 ns

, E

115 mA

80 mA

7.5 ns

12 ns

10 ns

-133

4 ns

), address burst

90 mA

65 mA

10 ns

15 ns

12 ns

-100

5 ns

64K x 32

1/23

Flow Through/Pipeline Reads

The function of the Data Output Register can be controlled by

the user via the FT mode pin (Pin 14 in the TQFP). Holding

the FT mode pin low places the RAM in Flow Through mode,

causing output data to bypass the Data Output Register.

Holding FT high places the RAM in Pipelined mode, activating

the rising-edge-triggered Data Output Register.

SCD Pipelined Reads

The GS82032A is an SCD (Single Cycle Deselect) pipelined

synchronous SRAM. DCD (Dual Cycle Deselect) versions are

also available. SCD SRAMs pipeline deselect commands one

stage less than read commands. SCD RAMs begin turning off

their outputs immediately after the deselect command has been

captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS82032A operates on a 3.3 V power supply and all

inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

from the internal circuit.

DDQ

) pins are used to decouple output noise

GS82032AT/Q-180/166/133/100

3.3 V and 2.5 V I/O

180 MHz–100 MHz

8 ns–12 ns

3.3 V V

Related parts for GS82032AT-6

GS82032AT-6 Summary of contents

Page 1

... The GS82032A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (V from the internal circuit address burst 2 3 1/23 GS82032AT/Q-180/166/133/100 180 MHz–100 MHz 8 ns– 3.3 V and 2.5 V I/O ) pins are used to decouple output noise DDQ © 2000, Giga Semiconductor, Inc. DD ...

Page 2

... DDQ Rev: 1.09 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT/Q-180/166/133/100 64K x 32 Top View 2/ ...

Page 3

... FT I Flow Through or Pipeline mode; active low LBO DDQ 3/23 GS82032AT/Q-180/166/133/100 Description Address Inputs Data Input and Output pins No Connect , DQ Data I/Os; active low Data I/Os; active low C D Clock Input Signal; active high Chip Enable; active low Chip Enable ...

Page 4

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q 4/23 GS82032AT/Q-180/166/133/100 A Memory Array – DQx1 DQx8 © 2000, Giga Semiconductor, Inc. ...

Page 5

... may be used in any combination with BW to write single or multiple bytes. D 5/23 GS82032AT/Q-180/166/133/100 Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby A[1:0] A[1:0] A[1:0] A[1: ...

Page 6

... X H None X L None Next CR X Next CR H Next CW X Next 6/23 GS82032AT/Q-180/166/133/100 2 ADSP ADSC ADV ...

Page 7

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. X Deselect First Write Burst Write 7/23 GS82032AT/Q-180/166/133/100 First Read Burst Read and Write ( BW, and GW) control ...

Page 8

... Input Set Up Time. Rev: 1.09 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. X Deselect First Write Burst Write 8/23 GS82032AT/Q-180/166/133/100 First Read Burst Read CR © 2000, Giga Semiconductor, Inc. ...

Page 9

... Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications quoted are evalu- ated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be –2 V > Vi < V Rev: 1.09 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS82032AT/Q-180/166/133/100 Value Unit –0.5 to 4.6 –0 – ...

Page 10

... Symbol Test conditions 3 OUT OUT Layer Board Symbol R single JA R four 10/23 GS82032AT/Q-180/166/133/100 20% tKC DD IL Typ. Max. Unit TQFP Max QFP Max Unit 40 TBD C/W 24 TBD C/W 9 TBD C/W © 2000, Giga Semiconductor, Inc. ...

Page 11

... V OUT –4 mA 2.375 DDQ –4 mA 3.135 DDQ 11/23 GS82032AT/Q-180/166/133/100 Output Load 2 2.5 V 225 DQ * 225 5pF Min Max – – –1 uA 300 uA –300 – – 1.7 V 2.4 V 0.4 V © ...

Page 12

... Pipeline I DD Flow 100 105 90 Through I SB Flow Through Pipeline I DD Flow Through 12/23 GS82032AT/Q-180/166/133/100 -133 -100 0 0 –40 to – 85°C 85°C 85°C 70°C 70°C 145 115 120 ...

Page 13

... GS82032AT/Q-180/166/133/100 -133 -100 Max Min Max Min Max — 7.5 — 10 — 3.5 — 4 — 5 — 1.5 — 1.5 — — 1.5 — 1.5 — — 12 — 15 — 8.5 — ...

Page 14

... ADSP 1 E and E only sampled with ADSP or ADSC Write specified byte for 14/23 GS82032AT/Q-180/166/133/100 Deselected Write inactive 1 ADSC initiated write WR3 WR3 WR3 Deselected with E and all bytes for & ...

Page 15

... E masks ADSP 1 E and E only sampled with ADSP or ADSC 2 3 tOHZ tOE tKQX 15/23 GS82032AT/Q-180/166/133/100 inactive 1 ADSC initiated read Suspend Burst RD3 tH tH Deselected with E tKQX tHZ © 2000, Giga Semiconductor, Inc. 2 ...

Page 16

... WR1 E2 and E3 only sampled with ADSP and ADSC tOHZ 16/23 GS82032AT/Q-180/166/133/100 Burst Read ADSP is blocked by E inactive E1 masks ADSP Deselected with Burst wrap around to it’s initial state © 2000, Giga Semiconductor, Inc. ...

Page 17

... E1 masks ADSP tH E and E only sampled with ADSP or ADSC tOE tOHZ tKQX tOLZ tLZ tKQ 17/23 GS82032AT/Q-180/166/133/100 inactive 1 ADSC initiated read Suspend Burst RD3 tH tH Deselected with E tKQX © 2000, Giga Semiconductor, Inc ...

Page 18

... RD2 WR1 WR1 E2 and E3 only sampled with ADSP and ADSC tOE tOHZ tS tH tKQ 18/23 GS82032AT/Q-180/166/133/100 Burst Read ADSP is blocked by E inactive E1 masks ADSP Deselected with © 2000, Giga Semiconductor, Inc ...

Page 19

... Rev: 1.09 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. tKC tKH tKL tZZH tZZS Snooze 19/23 GS82032AT/Q-180/166/133/100 tZZR © 2000, Giga Semiconductor, Inc. ...

Page 20

... PD LD Rev: 1.09 7/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com Out (Pull Dow Out (Pull Up) DDQ 20/23 GS82032AT/Q-180/166/133/100 V DDQ I Out VOut V SS 2.5 3 3 © 2000, Giga Semiconductor, Inc. ...

Page 21

... Min. Nom. Max Standoff 0.05 0.10 0.15 1.35 1.40 1.45 Lead Width 0.20 0.30 0.40 0.09 — 0.20 21.9 22.0 22.1 19.9 20.0 20.1 15.9 16.0 16.1 13.9 14.0 14.1 Lead Pitch — 0.65 — Foot Length 0.45 0.60 0.75 Lead Length — 1.00 — Coplanarity — — 0.10 Lead Angle 0 — 7 21/23 GS82032AT/Q-180/166/133/100 QFP Min. Nom. Max 0.25 0.35 0.45 2.55 2.72 2.90 0.20 0.30 0.40 0.10 0.15 0.20 22.95 23.2 23.45 19.9 20.0 20.1 17.0 17.2 17.4 13.9 14.0 14.1 — 0.65 — .60 0.80 1.00 — 1.60 — — — 0.10 0 — 7 © 2000, Giga Semiconductor, Inc. ...

Page 22

... GS82032AT-166I Pipeline/Flow Through 64K x 32 GS82032AT-133I Pipeline/Flow Through 64K x 32 GS82032AT-4I Pipeline/Flow Through 64K x 32 GS82032AT-5I Pipeline/Flow Through 64K x 32 GS82032AT-6I Pipeline/Flow Through 64K x 32 GS82032AQ-180 Pipeline/Flow Through 64K x 32 GS82032AQ-166 Pipeline/Flow Through 64K x 32 GS82032AQ-133 Pipeline/Flow Through 64K x 32 GS82032AQ-4 ...

Page 23

... Updated format to comply with Technical Publications standards • Added the following part numbers to the Ordering Information table on page 22: – GS82032AT-4 – GS82032AT-6 – GS82032AT-4I Content – GS82032AT-6I – GS82032AQ-4 – GS82032AQ-6 – GS82032AQ-4I – GS82032AQ-6I • Removed all references to 200 MHz parts (no longer active) Content 23/23 GS82032AT/Q-180/166/133/100 © ...

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