AT32UC3A464S Atmel Corporation, AT32UC3A464S Datasheet - Page 110

• Manufacturer Part Number: AT32UC3A464S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464S

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

11.6.2
Figure 11-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge
Figure 11-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge
32072G–11/2011
EXTINTn/NMI
EXTINTn/NMI
FILTER off
FILTER on
FILTER off
FILTER on
ISR.INTn:
ISR.INTn:
ISR.INTn:
ISR.INTn:
CLK_SYNC
CLK_SYNC
Synchronization and Filtering of External Interrupts
gate to the interrupt controller. However, the corresponding bit in ISR will be set, and
EIC_WAKE will be set.
If the CTRL.INTn bit is zero, then the corresponding bit in ISR will always be zero. Disabling an
external interrupt by writing to the DIS.INTn bit will clear the corresponding bit in ISR.
In synchronous mode the pin value of the EXTINTn pin is synchronized to CLK_SYNC, so
spikes shorter than one CLK_SYNC cycle are not guaranteed to produce an interrupt. The syn-
chronization of the EXTINTn to CLK_SYNC will delay the propagation of the interrupt to the
interrupt controller by two cycles of CLK_SYNC, see
on page 110
It is also possible to apply a filter on EXTINTn by writing a one to INTn bit in the FILTER register.
This filter is a majority voter, if the condition for an interrupt is true for more than one of the latest
three cycles of CLK_SYNC the interrupt will be set. This will additionally delay the propagation of
the interrupt to the interrupt controller by one or two cycles of CLK_SYNC, see
page 110
and
for examples (FILTER off).
Figure 11-3 on page 110
for examples (FILTER on).
Figure 11-2 on page 110
and
Figure 11-2 on
Figure 11-3
110