AT32UC3A464S Atmel Corporation, AT32UC3A464S Datasheet - Page 649
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AT32UC3A464S
Manufacturer Part Number
AT32UC3A464S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A464S
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A464S-U
Manufacturer:
ATMEL
Quantity:
551
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 649 of 1012
- Download datasheet (16Mb)
26.7.3.11
32072G–11/2011
RXINI
FIFOCON
IN
Management of OUT pipes
(bank 0)
DATA
RXINI
FIFOCON
RXINI shall be cleared by software (by writing a one to the Received IN Data Interrupt Clear bit
in the Pipe n Control Clear register(UPCONnCLR.RXINIC)) to acknowledge the interrupt, what
has no effect on the pipe FIFO.
The user then reads from the FIFO (see
DATA)” on page
(FIFOCONC) bit in UPCONnCLR) to free the bank. If the IN pipe is composed of multiple banks,
this also switches to the next bank. The RXINI and FIFOCON bits are updated in accordance
with the status of the next bank.
RXINI shall always be cleared before clearing FIFOCON.
The Read/Write Allowed (RWALL) bit in UPSTAn is set when the current bank is not empty, i.e.,
the software can read further data from the FIFO.
Figure 26-24. Example of an IN Pipe with 1 Data Bank
Figure 26-25. Example of an IN Pipe with 2 Data Banks
OUT packets are sent by the host. All the data can be written which acknowledges or not the
bank when it is full.
The pipe must be configured and unfrozen first.
IN
ACK
HW
(bank 0)
DATA
SW
740) and clears the FIFOCON bit (by writing a one to the FIFO Control Clear
read data from CPU
BANK 0
ACK
HW
SW
SW
read data from CPU
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
IN
BANK 0
IN
(bank 1)
DATA
(bank 0)
DATA
SW
ACK
HW
ACK
HW
read data from CPU
read data from CPU
SW
SW
BANK 1
BANK 0
649
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