AT32UC3A464S Atmel Corporation, AT32UC3A464S Datasheet - Page 615
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AT32UC3A464S
Manufacturer Part Number
AT32UC3A464S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A464S
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A464S-U
Manufacturer:
ATMEL
Quantity:
551
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 615 of 1012
- Download datasheet (16Mb)
25.8
25.8.1
32072G–11/2011
Module Configuration
Clock Connections
The specific configuration for each USART instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the Sys-
tem Bus Clock Connections section.
Table 25-27. Module Configuration
Table 25-28. Module Clock Name
Each USART can be connected to an internally divided clock:
Table 25-29. USART Clock Connections
Feature
SPI Logic
LIN Logic
Manchester Logic
Modem Logic
IRDA Logic
RS485 Logic
Fractional Baudrate
ISO7816
DIV value for divided CLK_USART
Receiver Time-out Counter Size
(Size of the RTOR.TO field)
Module name
USART0
USART1
USART2
USART3
USART
0
1
2
3
Clock name
CLK_USART0
CLK_USART1
CLK_USART2
CLK_USART3
Source
Internal
Name
CLK_DIV
USART0
USART2
USART3
Implemented
Implemented
Not Implemented
Not Implemented
Not Implemented
Not Implemented
Implemented
Not Implemented
8
8-bits
Description
Peripheral Bus clock from the PBA clock domain
Peripheral Bus clock from the PBA clock domain
Peripheral Bus clock from the PBA clock domain
Peripheral Bus clock from the PBA clock domain
Connection
PBA Clock / 8 (CLK_PBA_USART_DIV)
PBA Clock / 8 (CLK_PBA_USART_DIV)
PBA Clock / 8 (CLK_PBA_USART_DIV)
PBA Clock / 8 (CLK_PBA_USART_DIV)
USART1
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
8
17-bits
615
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