AT32UC3A464S Atmel Corporation, AT32UC3A464S Datasheet - Page 232
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AT32UC3A464S
Manufacturer Part Number
AT32UC3A464S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A464S
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A464S-U
Manufacturer:
ATMEL
Quantity:
551
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 232 of 1012
- Download datasheet (16Mb)
16.8.1
Register Name:
Access Type:
Offset:
Reset Value:
• MODE: Command Mode
32072G–11/2011
MODE
0
1
2
3
4
5
6
31
23
15
7
-
-
-
-
This field defines the command issued by the SDRAMC when the SDRAM device is accessed.
Mode Register
Description
Normal mode. Any access to the SDRAM is decoded normally.
The SDRAMC issues a “NOP” command when the SDRAM device is accessed regardless of the cycle.
The SDRAMC issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of
the cycle.
The SDRAMC issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the
cycle. This command will load the CR.CAS field into the SDRAM device Mode Register. All the other parameters
of the SDRAM device Mode Register will be set to zero (burst length, burst type, operating mode, write burst
mode...).
The SDRAMC issues an “Auto Refresh” command when the SDRAM device is accessed regardless of the cycle.
Previously, an “All Banks Precharge” command must be issued.
The SDRAMC issues an “Extended Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. This command will load the LPR.PASR, LPR.DS, and LPR.TCR fields into the SDRAM
device Extended Mode Register. All the other bits of the SDRAM device Extended Mode Register will be set to
zero.
Deep power-down mode. Enters deep power-down mode.
30
22
14
6
-
-
-
-
MR
Read/Write
0x00
0x00000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
-
26
18
10
2
-
-
-
MODE
25
17
9
1
-
-
-
24
16
8
0
-
-
-
232
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