AT32UC3A464S Atmel Corporation, AT32UC3A464S Datasheet - Page 888
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AT32UC3A464S
Manufacturer Part Number
AT32UC3A464S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A464S
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A464S-U
Manufacturer:
ATMEL
Quantity:
551
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 888 of 1012
- Download datasheet (16Mb)
Figure 32-3. DMA Mode when MR.LOD is zero
Figure 32-4. DMA Mode when MR.LOD is one
Table 32-3.
Note:
Warning: In DMA mode, reading to the ODATAnR registers before the last data transfer may lead to unpredictable results.
32072G–11/2011
Encryption/Decryption
Encrypted/Decrypted
Data Result Location
Clearing Condition
ISR.DATRDY bit
1. Depending on the mode, there are other ways of clearing the DATRDY.ISR bit. See the Interrupt Status Register (ISR)
End of
definition.
Last Output Mode Behavior versus Start Modes
(1)
The user must first wait for the DMA Controller Interrupt, then for ISR.DATRDY to ensure that
the encryption/decryption is completed.
In this case, no receive buffers are required.
The output data is only available in ODATAnR registers.
Following table summarizes the different cases.
D M A C o n tro lle r In te rru p t
DMA Controller Interrupt
At least one ODATAnR
In ODATAnR registers
register must be read
• when MR.LOD is one
ISR.DATRDY
MR.LOD = 0
ISR.DATRDY
Manual and Automatic Modes
E n a b le D M A C o n tro lle r C h a n n e ls (R e ce ive a n d T ra n sm it C h a n n e ls )
Enable DMA Controller Channels (only Transmit Channel)
register must be written
In ODATAnR registers
At least one IDATAnR
Multiple Encryption or Decryption Processes
M u ltip le e n cryp tio n o r d e c ryp tio n p ro ce ss e s
ISR.DATRDY
MR.LOD = 1
DMA Controller
configuration of
DMA Controller
specified in the
At the address
MR.LOD = 0
Not used
Interrupt
DMA Mode
Managed by the
In ODATAnR registers
DMA Controller
Interrupt then
DATRDY.ISR
MR.LOD = 1
Controller
DMA
888
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