AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 186

• Manufacturer Part Number: AT32UC3C0256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

186
AVR32
LD.W – Load Word
Architecture revision:
Architecture revision1 and higher.
Description
Format I to V: Reads the word memory location specified.
Format VI: This instruction extracts a specified byte from Ri. This value is zero-extended, shifted
left two positions and added to Rb to form an address. The contents of this address is loaded
into Rd. The instruction is useful for indexing tables.
Operation:
I.
II.
III.
IV.
V.
VI.
Syntax:
I.
II.
III.
IV.
V.
VI.
Operands:
I-V.
III.
IV.
V.
VI.
Rd ← *(Rp);
Rp ← Rp + 4;
Rp ← Rp - 4;
Rd ← *(Rp);
Rd ← *(Rp + (ZE(disp5) << 2));
Rd ← *(Rp + (SE(disp16)));
Rd ← *(Rb + (Ri << sa2));
If (part == b)
else if (part == l)
else if (part == u)
else
ld.w
ld.w
ld.w
ld.w
ld.w
ld.w
d, p, b, i ∈ {0, 1, …, 15}
disp ∈ {0, 4, ..., 124}
disp ∈ {-32768, -32767, ..., 32767}
sa ∈ {0, 1, 2, 3}
{d, b, i} ∈ {0, 1, …, 15}
part ∈ {t, u, l, b}
Rd ← *(Rb + (Ri[7:0] << 2) );
Rd ← *(Rb + (Ri[15:8] << 2) );
Rd ← *(Rb + (Ri[23:16] << 2) );
Rd ← *(Rb + (Ri[31:24] << 2) );
Rd, Rp++
Rd, --Rp
Rd, Rp[disp]
Rd, Rp[disp]
Rd, Rb[Ri<<sa]
Rd, Rb[Ri:<part> << 2]
32000D–04/2011