AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 57

• Manufacturer Part Number: AT32UC3C0256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7. Performance counters
7.1
7.2
7.2.1
7.2.2
7.2.3
32000D–04/2011
Overview
Registers
Performance clock counter - PCCNT
Performance counter 0,1 - PCNT0, PCNT1
Performance counter control register - PCCR
A set of performance counters let users evaluate the performance of the system. This is useful
when scheduling code and performing optimizations. Two configurable event counters are pro-
vided in addition to a clock cycle counter. These three counters can be used to collect
information about for example cache miss rates, branch prediction hit rate and data hazard stall
cycles.
The three counters are implemented as 32-bit registers accessible through the system register
interface. They can be configured to issue an interrupt request in case of overflow, allowing a
software overflow counter to be implemented.
A performance counter control register is implemented in addition to the three counter registers.
This register controls which events to record in the counter, counter overflow interrupt enable
and other configuration data.
This register counts CPU clock cycles. When it reaches 0xFFFF_FFFF, it rolls over. The over-
flow flag is set and an exception is generated if configured by PCCR. The register can be reset
by writing to the C bit in PCCR. PCCNT can be preset to a value by writing directly to it. PCCNT
is written to zero upon reset.
These counters monitor events as configured by PCCR. When they reach 0xFFFF_FFFF, they
roll over. The overflow flag is set and an exception is generated if configured by PCCR. The reg-
isters can be reset by writing the R bit in PCCR. The registers can be preset to a value by writing
directly to them. PCNT0 and PCNT1 are written to zero upon reset.
This register controls the behaviour of the entire performance counter system, see
page
zero upon reset.
Figure 7-1.
31
57. This register is read and written by the mtsr and mfsr instructions. PCCR is written to
-
Performance counter control register
24
23
CONF1
18
17
CONF0
12
-
10
F
8
-
6
IE
4
Figure 7-1 on
AVR32
3
S
2
C
1
R
0
E
57