AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet
AT32UC3C0256C
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AT32UC3C0256C Summary of contents
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... One 2-channel Controller Area Network (CAN) – CAN2A and CAN2B protocol compliant, with high-level mailbox system – Two independent channels, 16 Message Objects per Channel ® Microcontroller ® 32-bit AVR Microcontroller AT32UC3C0512C AT32UC3C0256C AT32UC3C0128C AT32UC3C064C AT32UC3C1512C AT32UC3C1256C AT32UC3C1128C AT32UC3C164C AT32UC3C2512C AT32UC3C2256C AT32UC3C2128C AT32UC3C264C 32117C– ...
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One 4-Channel 20-bit Pulse Width Modulation Controller (PWM) – Complementary outputs, with Dead Time Insertion – Output Override and Fault Protection • Two Quadrature Decoders • One 16-channel 12-bit Pipelined Analog-To-Digital Converter (ADC) – Dual Sample and Hold Capability ...
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Description The AT32UC3C is a complete System-On-Chip microcontroller based on the AVR32UC RISC processor running at frequencies MHz. AVR32UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular empha- sis on ...
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The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device like a USB Flash disk or a USB printer to be directly connected ...
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Overview 2.1 Block diagram Figure 2- 32117C–AVR-08/11 Block diagram aWire RESET_N TDO JTAG TCK NEXUS TDI INTERFACE TMS CLASS 2+ MEMORY PROTECTION UNIT MCKO OCD MDO[5..0] INSTR MSEO[1..0] INTERFACE EVTI_N EVTO_N VBUS D+ USB D- ...
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... Ethernet MAC 10/100 I2S Asynchronous Timers Timer/Counter Channels PWM channels QDEC Frequency Meter Watchdog Timer Power Manager Oscillators 12-bit ADC number of channels 12-bit DAC number of channels 32117C–AVR-08/11 Configuration Summary AT32UC3C0512C/ AT32UC3C0256C/ AT32UC3C0128C/ AT32UC3C064C 512/256/128/64 KB 64/64/32/16KB 1 123 RMII/MII ...
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... Table 2-1. Feature Analog Comparators JTAG aWire Max Frequency Package 32117C–AVR-08/11 Configuration Summary AT32UC3C0512C/ AT32UC3C0256C/ AT32UC3C0128C/ AT32UC3C064C 4 LQFP144 AT32UC3C AT32UC3C1512C/ AT32UC3C2512C/ AT32UC3C1256C/ AT32UC3C2256C/ AT32UC3C1128C/ AT32UC3C2128C/ AT32UC3C164C AT32UC3C264C MHz TQFP100 TQFP64/QFN64 7 ...
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Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Figure 3-1. QFN64/TQFP64 Pinout Note: 32117C–AVR-08/11 on QFN packages, the exposed pad is unconnected. AT32UC3C Table 3-1 on page 11. 8 ...
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Figure 3-2. TQFP100 Pinout 32117C–AVR-08/11 AT32UC3C 9 ...
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Figure 3-3. LQFP144 Pinout 32117C–AVR-08/11 AT32UC3C 10 ...
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Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller Function Multiplexing TQFP ...
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Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN PA19 PA20 PA21 PA22 22 22 ...
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Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN O 14 PB11 43 15 PB12 44 16 PB13 45 17 PB14 46 18 PB15 47 19 PB16 48 20 PB17 49 ...
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Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN PC02 PC03 PC04 PC05 69 57 ...
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Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN PC24 88 98 PC25 89 99 PC26 90 100 PC27 91 101 PC28 92 102 PC29 93 105 PC30 ...
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Table 3-1. GPIO Controller Function Multiplexing TQFP QFN TQFP LQFP I 64 100 144 PIN O 124 PD15 111 125 PD16 112 126 PD17 113 127 PD18 114 128 PD19 115 129 PD20 116 57 88 130 ...
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Table 3-2. Function aWire DATAOUT JTAG port connections Oscillators 3.2.3 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF ...
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OCD AXS register. For details, see the AVR32UC Techni- cal Reference Manual. Table 3-5. Pin EVTI_N MDO[5] MDO[4] MDO[3] MDO[2] MDO[1] MDO[0] EVTO_N MCKO MSEO[1] MSEO[0] 3.2.6 Other Functions The functions listed in pin ...
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Table 3-7. Signal Description List Signal Name Function VDDIN_5 1.8V Voltage Regulator Input VDDIN_33 USB I/O power supply VDDCORE 1.8V Voltage Regulator Output GNDIO1 GNDIO2 I/O Ground GNDIO3 GNDANA Analog Ground GNDCORE Ground of the core GNDPLL Ground of the ...
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Table 3-7. Signal Description List Signal Name Function Analog negative reference connected to ADCVREFN external capacitor MCKO Trace Data Output Clock MDO[5:0] Trace Data Output MSEO[1:0] Trace Frame Control EVTI_N Event In EVTO_N Event Out DATA aWire data DATAOUT aWire ...
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Table 3-7. Signal Description List Signal Name Function SDCK SDRAM Clock SDCKE SDRAM Clock Enable SDWE SDRAM Write Enable EXTINT[8:1] External Interrupt Pins NMI_N = EXTINT[0] Non-Maskable Interrupt Pin General Purpose Input/Output - GPIOA, GPIOB, GPIOC, GPIOD PA[29:19] - PA[16:0] ...
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Table 3-7. Signal Description List Signal Name Function RX_CLK Receive Clock RX_DV Receive Data Valid RX_ER Receive Coding Error SPEED Speed TXD[3:0] Transmit Data TX_CLK Transmit Clock or Reference Clock TX_EN Transmit Enable TX_ER Transmit Coding Error WOL Wake-On-LAN PAD_EVT[15:0] ...
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Table 3-7. Signal Description List Signal Name Function NPCS[3:0] SPI Peripheral Chip Select SCK Clock A0 Channel 0 Line A A1 Channel 1 Line A A2 Channel 2 Line A B0 Channel 0 Line B B1 Channel 1 Line B ...
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Table 3-7. Signal Description List Signal Name Function DP USB Device Port Data + VBUS USB VBUS Monitor and OTG Negociation ID ID Pin of the USB Bus VBOF USB VBUS On/off: bus power control port 3.4 I/O Line Considerations ...
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Processor and Architecture Rev: 2.1.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see ...
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Load and store instructions have several different formats in order to reduce code size and speed up execution. The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack ...
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Figure 4-1. Instruction memory controller 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) ...
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Figure 4-2. 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt ...
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Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically ...
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Programming Model 4.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC ...
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Figure 4-5. Bit 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Priority N/A N/A Mode changes can ...
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Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 Secure State The AVR32 can be set in a secure state, that allows a part of the code ...
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Table 4-3. Reg # 33- ...
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Table 4-3. Reg # 100 101 102 103 104 105 106 107 108 109 110 111 112-191 192-255 4.5 Exceptions and Interrupts In the AVR32 architecture, events are used as ...
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EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments ...
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Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism ...
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An instruction B is younger than an instruction was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in the exceptions are unused in AVR32UC since ...
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Table 4-4. Priority and Handler Addresses for Events Priority Handler Address 1 0x80000000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...
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Memories 5.1 Embedded Memories • Internal High-Speed Flash (See – 512 Kbytes – 256 Kbytes – 128 Kbytes – 64 Kbytes • Internal High-Speed SRAM, Single-cycle access at full speed (See – 64 Kbytes – 32 Kbytes – 16 ...
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Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32UC CPU uses unsegmented translation, as described ...
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... Table 5-2. Part Number AT32UC3C0512C AT32UC3C1512C AT32UC3C2512C AT32UC3C0256C AT32UC3C1256C AT32UC3C2256C AT32UC3C0128C AT32UC3C1128C AT32UC3C2128C AT32UC3C064C AT32UC3C164C AT32UC3C264C 5.3 Peripheral Address Map Table 5-3. Peripheral Address Mapping Address 0xFFFD0000 0xFFFD1000 0xFFFD1400 0xFFFD1800 0xFFFD1C00 0xFFFD2000 0xFFFD2400 0xFFFD2800 0xFFFD2C00 0xFFFD3000 32117C–AVR-08/11 Flash Memory Parameters Number of Flash Size ...
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Table 5-3. Peripheral Address Mapping 0xFFFE0000 0xFFFE1000 0xFFFE2000 0xFFFE2400 0xFFFE2800 0xFFFE2C00 0xFFFE3000 0xFFFF0000 0xFFFF0400 0xFFFF0800 0xFFFF0C00 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF2000 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 32117C–AVR-08/11 HFLASHC Flash Controller - HFLASHC USBC USB 2.0 OTG Interface - USBC HMATRIX HSB Matrix ...
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Table 5-3. Peripheral Address Mapping 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 0xFFFF4800 0xFFFF4C00 0xFFFF5000 0xFFFF5400 0xFFFF5800 0xFFFF5C00 0xFFFF6000 0xFFFF6400 0xFFFF6800 0xFFFF6C00 0xFFFF7000 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, ...
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The following GPIO registers are mapped on the local bus: Table 5-4. Port 32117C–AVR-08/11 Local bus mapped GPIO registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register ...
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Table 5-4. Port D 32117C–AVR-08/11 Local bus mapped GPIO registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) AT32UC3C Local Bus Mode Address Access WRITE 0x40000340 Write-only SET 0x40000344 Write-only CLEAR 0x40000348 Write-only TOGGLE ...
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Supply and Startup Considerations 6.1 Supply Considerations 6.1.1 Power Supplies The AT32UC3C has several types of power supply pins: • VDDIO pins (VDDIO1, VDDIO2, VDDIO3): Power I/O lines. Two voltage ranges are available 3.3V nominal. The VDDIO ...
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The 3.3V regulator is connected to the 5V source (VDDIN_5 pin) and its output feeds the USB pads. If the USB is not used, the 3.3V regulator can be disabled through the VREG33CTL field of the VREGCTRL SCIF register. Figure ...
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Figure 6-2. C IN2 6.1.4 Power-up Sequence 6.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Recommended order for power supplies is also described in this ...
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Startup Considerations This chapter summarizes the boot sequence of the AT32UC3C. The behavior after power-up is controlled by the Power Manager. For specific details, refer to the Power Manager chapter. 6.2.1 Starting of clocks At power-up, the BOD33 and ...
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Power Manager (PM) Rev: 4.1.2.3 7.1 Features • Generates clocks and resets for digital logic • On-the-fly frequency change of CPU, HSB and PBx clocks • Sleep modes allow simple disabling of logic clocks and clock sources • Module-level ...
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Block Diagram Figure 7-1. PM Block Diagram Main Clock Sources Reset Sources Power-On Detector External Reset Pin 7.4 I/O Lines Description Table 7-1. I/O Lines Description Name Description RESET_N Reset 7.5 Product Dependencies 7.5.1 Interrupt The PM interrupt line ...
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Functional Description 7.6.1 Synchronous Clocks The System RC Oscillator (RCSYS set of other clock sources provide the source for the main clock, which is the common root for the synchronous clocks for the CPU/HSB and PBx modules. ...
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Similarly, the clock for the PBx can be divided by writing their respective registers. To ensure correct operation, frequencies must be selected so that f exceed the specified maximum frequency for each clock domain. CPUSEL and PBxSEL can be written ...
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The CPU and affected modules are restarted when the sleep mode is exited. This occurs when an interrupt triggers. Note that even if an interrupt is enabled in sleep mode, it may not trigger if the source module is not ...
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Table 7-3. Index 7.6.3.4 Precautions when entering sleep mode Modules communicating with external circuits should normally be disabled before entering a sleep mode that will stop the module operation. This prevents erratic behavior when entering ...
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Figure 7- addition to the listed reset types, the JTAG & AWIRE can keep parts of the device statically reset. See JTAG and AWIRE documentation for details. Table 7-4. Reset source Power-on Reset External ...
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Power-On Detector The Power-On Detector monitors the VDDCORE supply pin and generates a reset when the device is powered on. The reset is active until the supply voltage from the linear regulator is above the power-on threshold level. The ...
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User Interface Table 7-5. PM Register Memory Map Offset 0x0000 0x0004 0x0008 0x000C 0x00010 0x0014 0x0020 0x0024 0x0028 0x002C 0x0030 0x0040 0x0044 0x0048 0x0054 Clock Failure Detector Control 0x0058 0x00C0 PM Interrupt Enable Register 0x00C4 PM Interrupt Disable Register ...
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Main Clock Control Name: MCCTRL Access Type: Read/Write Offset: 0x0000 Reset Value: 0x00000000 • MCSEL: Main Clock Select Table 7-6. Main clocks in ...
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CPU Clock Select Name: CPUSEL Access Type: Read/Write Offset: 0x0004 Reset Value: 0x00000000 CPUDIV - • CPUDIV, CPUSEL: CPU Division and Clock Select • CPUDIV ...
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HSB Clock Select Name: HSBSEL Access Type: Read Only Offset: 0x0008 Reset Value: 0x00000000 HSBDIV - This register is read-only and its content is always ...
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PBx Clock Select Name: PBxSEL Access Type: Read/Write Offset: 0x000C, 0x0010, 0x0014 Reset Value: 0x00000000 PBDIV - • PBDIV, PBSEL: PBx Division and Clock Select ...
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Clock Mask Name: CPU/HSB/PBA/PBBMASK Access Type: Read/Write Offset: 0x0020, 0x0024, 0x0028, 0x002C, 0x0030 Reset Value • MASK: Clock Mask • If bit n is cleared, the clock for module n ...
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Table 7-7. Maskable module clocks in AT32UC3C. Bit CPUMASK 31:27 - Note ...
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Divided Clock Mask Name: PBADIVMASK/PBBDIVMASK/PBCDIVMASK Access Type: Read/Write Offset: 0x0040, 0x0044, 0x0048 Reset Value • MASK: Clock Mask If bit n is written to ...
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Table 7-9. Bit Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 32117C–AVR-08/11 PBC Divided ...
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Clock Failure Detector Control Register Name: CFDCTRL Access Type: Read/Write Offset: 0x0054 Reset Value: 0x00000000 31 30 SFV - • SFV: Store Final Value • 0: The ...
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PM Unlock Register Name: UNLOCK Access Type: Write-Only Offset: 0x0058 Reset Value unlock a write protected register, first write to the UNLOCK register with the ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x0C0 Reset Value: 0x00000000 Writing a zero to a bit in this register has ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x0C4 Reset Value: 0x00000000 Writing a zero to a bit in this register has ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x0C8 Reset Value: 0x00000000 The corresponding interrupt is disabled. 1: The corresponding interrupt ...
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Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x0CC Reset Value: 0x00000000 The corresponding interrupt is cleared. 1: The corresponding interrupt ...
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Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x0D0 Reset Value: 0x00000000 Writing a zero to a bit in this register has ...
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Status Register Name: SR Access Type: Read-only Offset: 0x0D4 Reset Value: 0x00000000 • AE: Access Error 0: No access error has occured. 1: ...
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Reset Cause Name: RCAUSE Access Type: Read-only Offset: 0x0180 Reset Value: Latest Reset Source CPUERR • BOD33: Brown-out 3.3V reset The CPU was reset due ...
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Wake Cause Register Register name WCAUSE Register access Read-only Offset: 0x0184 Reset Value: Latest Reset Source • A bit in this register is set on wake up ...
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Asynchronous Wake Up Enable Register Register name AWEN Register access Read/Write Offset: 0x0188 Reset Value: 0x00000000 Each bit in this register corresponds to an asynchronous wake up, according to 0: The ...
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Configuration Register Name: CONFIG Access Type: Read-Only Offset: 0x03F8 Reset Value: 0x000000C3 HSBPEVC This register shows the configuration of the PM. • HSBPEVC:HSB PEVC Clock ...
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Version Register Name: VERSION Access Type: Read-Only Offset: 0x03FC Reset Value: 0x00000410 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version ...
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Module Configuration The specific configuration for each PM instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 7-12. ...
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System Control Interface (SCIF) Rev: 1.0.2.0 8.1 Features • Controls integrated oscillators and PLLs • Supports 2x General Purpose crystal oscillators, 0.4MHz-20MHz • Supports 2x Phase-Locked-Loop, 80-240 MHz • Supports 32 KHz low power oscillator (OSC32K) • Integrated 115KHz ...
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Interrupt The SCIF interrupt line is connected to one of the internal sources of the interrupt controller. Using the SCIF interrupt requires the interrupt controller to be programmed first. 8.4.3 Debug Operation The SCIF module does not interact with ...
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Figure 8-1. UC3C C i 8.5.2 32KHz Oscillator (OSC32K) Operation The 32 KHz oscillator (OSC32K) operates as described for the Oscillator above. The 32 KHz oscillator is used as source clock for the Asynchronous Timer and the Watchdog Timer. The ...
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Figure 8-2. Osc0 clock 0 1 Osc1 clock PLLOSC 8.5.3.1 Enabling the PLL PLLn is enabled by writing a one to the PLLEN bit in the PLLn register. PLLOSC selects Oscilla- tor clock source. The PLLMUL ...
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Figure 8-3. OSCSEL 8.5.4.1 Enabling a generic clock A generic clock is enabled by writing a one to the CEN bit in GCCTRL to one. Each generic clock can individually select a clock source by setting the OSCSEL bits. The ...
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Table 8-2. Clock number 8.5.5 1.8V Brown Out Detection (BOD18) The 1.8V Brown-Out Detector (BOD18) monitors the VDDCORE supply pin and compares the supply voltage to the brown-out detection level, as set in BOD.LEVEL. The BOD18 is disabled by default, ...
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If the JTAG or the AWIRE is enabled, the BOD33 reset and interrupt will be masked. See Electrical Characteristics for parametric details. To prevent unexpected writes due to software bugs, write access to this register is protected by a locking ...
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System RC Oscillator (RCSYS) The system RC oscillator (RCSYS) has a 3 cycles startup time, and is always available except in the STATIC sleep mode. The system RC oscillator operates at a nominal frequency of 115 kHz, and is ...
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BOD50DET - 5V Brown out detection: – Set when transition on the PCLKSR.BOD50DET bit is detected. • BOD33DET - 3.3V Brown out detection: – Set when transition on the PCLKSR.BOD33DET bit ...
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User Interface Table 8-3. SCIF Register Memory Map Offset 0x0000 Interrupt Enable Register 0x0004 Interrupt Disable Register 0x0008 Interrupt Mask Register 0x000C Interrupt Status Register 0x0010 Interrupt Clear Register 0x0014 Power and Clocks Status Register 0x0018 0x001C PLL0 Control ...
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Table 8-3. SCIF Register Memory Map Offset 0x03F4 GPLP Version Register 0x03F8 Generic Clock Version Register 0x03FC SCIF Version Register Note: 32117C–AVR-08/11 Register Register Name GPLPVERSION GCLKVERSION 1. The reset value is device specific. Please refer to the Module Configuration ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x0000 Reset Value: 0x00000000 BOD33DET BODDET PLL1_LOCK Writing a zero to a bit in this register ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x0004 Reset Value: 0x00000000 BOD33DET BODDET PLL1_LOCK Writing a zero to a bit in this register ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x0008 Reset Value: 0x00000000 BOD33DET BODDET PLL1_LOCK 0: The corresponding interrupt is disabled. 1: The corresponding ...
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Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x000C Reset Value: 0x00000000 BOD33DET BODDET PLL1_LOCK 0: The corresponding interrupt is cleared. 1: The corresponding ...
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Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x0010 Reset Value: 0x00000000 BOD33DET BODDET PLL1_LOCK Writing a zero to a bit in this register ...
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Power and Clocks Status Register Name: PCLKSR Access Type: Read-Only Offset: 0x0014 Reset Value: 0x00000000 BOD33DET BODDET PLL1_LOCK • AE: SCIF Access Error 0: No ...
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RCOSC8MRDY: 8MHz / 1MHz RCOSC Ready 0: 8MHz / 1MHz RC Oscillator not enabled or not ready. 1: 8MHz / 1MHz RC Oscillator is stable and ready to be used as clock source. • OSC32RDY: 32 KHz oscillator Ready ...
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Unlock Register Name: UNLOCK Access Type: Write-Only Offset: 0x0018 Reset Value: 0x00000000 unlock a write protected register, first write to the UNLOCK register with the address ...
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PLL Control Register Name: PLL0,1 Access Type: Read/Write Offset: 0x001C,0x0020 Reset Value: 0x00000000 • PLLCOUNT: PLL Count Specifies the number of slow clock ...
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Table 8-4. PLLOPT[0]: VCO frequency PLLOPT[1]: Output divider PLLOPT[2] • PLLOSC: PLL Oscillator Select 0: Oscillator 0 is the source for the PLL. 1: Oscillator 1 is the source for the PLL. 2: 8MHz/1MHz RCOSC is the source for the ...
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Oscillator Control Register Name: OSCCTRL0,1 Access Type: Read/Write Offset: 0x0024,0x0028 Reset Value: 0x00000000 • OSCEN 0: Disable the Oscillator. 1: Enable the Oscillator. ...
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Table 8-5. Startup time for oscillators 0 and 1 Number of RC oscillator clock STARTUP cycle 13 512 14 1024 15 Reserved • AGC: Automatic Gain Control 0: Disable the automatic gain control of the Oscillator. 1: Enable the automatic ...
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BOD Control Register Name: BOD Access Type: Read/Write Offset: 0x002C Reset Value: 0x00000000 31 30 SFV - HYST • SFV: Store Final Value 0: The register is ...
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LEVEL: BOD18 Level This field sets the triggering threshold of the BOD18. See Electrical Characteristics for actual voltage levels. Note that any change to the LEVEL field of the BOD register should be done with the BOD18 deactivated to ...
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Bandgap Calibration Register Name: BGCR Access Type: Read/Write Offset: 0x0030 Reset Value: 0x00000000 31 30 SFV - • SFV: Store Final Value 0: The register is read/write. ...
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BOD Control Register Name: BOD33 Access Type: Read/Write Offset: 0x0034 Reset Value: 0x00000000 31 30 SFV - HYST • SFV: Store Final Value 0: The register is ...
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LEVEL: BOD33 Level This field sets the triggering threshold of the BOD33. See Electrical Characteristics for actual voltage levels. Note that any change to the LEVEL field of the BOD33 register should be done with the BOD33 deactivated to ...
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BOD Control Register Name: BOD50 Access Type: Read/Write Offset: 0x0038 Reset Value: 0x00000000 31 30 SFV - HYST • SFV: Store Final Value 0: The register is ...
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Voltage Regulator Calibration Register Name: VREGCR Access Type: Read/Write Offset: 0x003C Reset Value: 0x00000000 31 30 SFV - • SFV: Store Final Value 0: The register is ...
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Voltage Regulator Control Register Name: VREGCTRL Access Type: Read/Write Offset: 0x0040 Reset Value: 0x00000000 31 30 SFV - • SFV: Store Final Value 0: The register is ...
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RCSYS Calibration Register Name: RCCR Access Type: Read/Write Offset: 0x0044 Reset Value: 0x00000000 • FCD: Flash Calibration Done Set to 1 when CALIB field has ...
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RC Oscillator Control Register Name: RCCR8 Access Type: Read/Write Offset: 0x0048 Reset Value: 0x00000000 • FREQMODE: Frequency Mode 0: the RC8M RC ...
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Oscillator Control Register Name: OSCCTRL32 Access Type: Read/Write Offset: 0x004C Reset Value: 0x00000000 Note: This register is only reset by Power-On Reset. ...
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MODE: Oscillator Mode Table 8-11. Operation mode for 32 KHz oscillator MODE Description 0 External clock connected to XIN32, XOUT32 can be used as I/O (no crystal) 1 2-pin crystal mode. Crystal is connected to XIN32/XOUT32 2 2-pin crystal ...
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RC Oscillator Control Register Name: RC120MCR Access Type: Read/Write Offset: 0x0058 Reset Value: 0x00000000 • EN: RC120M Enable 0: Clock is stopped. ...
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General Purpose Low-power Register 0/1 Name: GPLP0,1 Access Type: Read/Write Offset: 0x005C,0x0060 Reset Value: 0x00000000 These registers are general purpose 32-bit registers that are reset only by power-on-reset. Any other reset ...
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Generic Clock Control Name: GCCTRL Access Type: Read/Write Offset: 0x0064-0x008C Reset Value: 0x00000000 There is one GCCTRL register per generic clock in the device. • DIV: Division ...
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DIVEN: Divide Enable 0: The generic clock equals the undivided source clock. 1: The generic clock equals the source clock divided by 2*(DIV+1). • CEN: Clock Enable 0: Clock is stopped. 1: Clock is running. 32117C–AVR-08/11 AT32UC3C 119 ...
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PLL Interface Version Register Name: PLLVERSION Access Type: Read-Only Offset: 0x03C8 Reset Value • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version ...
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Oscillator Interface Version Register Name: OSCVERSION Access Type: Read-Only Offset: 0x03CC Reset Value • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version ...
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BOD Interface Version Register Name: BODVERSION Access Type: Read-Only Offset: 0x03D0 Reset Value • VARIANT: Variant number Reserved. No functionality associated. • VERSION: ...
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BOD Interface Version Register Name: BODBVERSION Access Type: Read-Only Offset: 0x03D4 Reset Value • VARIANT: Variant number Reserved. No functionality associated. ...
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Voltage Regulator Interface Version Register Name: VREGVERSION Access Type: Read-Only Offset: 0x03D8 Reset Value • VARIANT: Variant number Reserved. No functionality associated. • VERSION: ...
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RCSYS Interface Version Register Name: RCCRVERSION Access Type: Read-Only Offset: 0x03DC Reset Value • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version ...
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RCOSC Interface Version Register Name: RCCR8VERSION Access Type: Read-Only Offset: 0x03E0 Reset Value • VARIANT: Variant number Reserved. No functionality associated. ...
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Oscillator Interface Version Register Name: OSC32VERSION Access Type: Read-Only Offset: 0x03E4 Reset Value • VARIANT: Variant number Reserved. No functionality associated. • VERSION: ...
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RC Oscillator Version Register Name: RC120MVERSION Access Type: Read-Only Offset: 0x03F0 Reset Value • VARIANT: Variant number Reserved. No functionality associated. • VERSION: ...
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GPLP Version Register Name: GPLPVERSION Access Type: Read-Only Offset: 0x03F4 Reset Value • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number ...
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Generic Clock Version Register Name: GCLKVERSION Access Type: Read-Only Offset: 0x03F8 Reset Value • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version ...
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SCIF Version Register Name: VERSION Access Type: Read-Only Offset: 0x03FC Reset Value • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number ...
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Module Configuration The specific configuration for each SCIF instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man- ager chapter for details. Table ...
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Asynchronous Timer (AST) Rev: 2.0.0.1 9.1 Features • 32-bit counter with 32-bit prescaler • Clocked Source – System RC oscillator (RCSYS) – 32KHz crystal oscillator (OSC32K) – PB clock – Generic clock (GCLK) – 1KHz clock from 32KHz oscillator ...
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Block Diagram Figure 9-1. Asynchronous Timer block diagram CONTROL REGISTER CLK_AST CSSEL 32 KHz RC OSC CLK_AST_PRSC PB clock GCLK DIGITAL TUNER REGISTER 9.4 Product Dependencies In order to use this module, other parts of the system must be ...
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Peripheral Bus clock (PB clock). This is the clock of the peripheral bus the AST is connected to. • Generic clock (GCLK). One of the generic clocks is connected to the AST. This clock must be enabled before use, ...
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Changing the source clock The CLK_AST_PRSC must be disabled before switching to another source clock. The Clock Busy bit in the Status Register (SR.CLKBUSY) indicates whether the clock is busy or not. This bit is set when the CEN ...
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Calendar operation When the CAL bit in the Control Register is one, the counter operates in calendar mode. Before this mode is enabled, the prescaler should be set up to give a pulse every second. The date and time ...
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AST is enabled. The bit is selected by the Interval Select field in the corre- sponding Periodic Interval Register (PIRn.INSEL), resulting in a periodic interrupt frequency of where f The corresponding PERn bit in the Status Register ...
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The peripheral event will be generated if the corresponding bit in the Event Mask (EVM) register is set. Bits in EVM register are set by writing a one to the corresponding bit in the Event Enable (EVE) register, and cleared ...
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Synchronization As the prescaler and counter operate asynchronously from the user interface, the AST needs a few clock cycles to synchronize values written to the CR, CV, SCR, WER, EVE, EVD, PIRx, ARx and DTR registers. The Busy bit ...
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User Interface Table 9-1. AST Register Memory Map Offset 0x00 Control Register 0x04 0x08 0x0C Status Clear Register 0x10 Interrupt Enable Register 0x14 Interrupt Disable Register 0x18 Interrupt Mask Register 0x1C Wake Enable Register 0x20 Alarm Register 0 0x24 ...
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Control Register Name: CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 When the SR.BUSY bit is set, writes to this register will ...
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Counter Value Name: CV Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 When the SR.BUSY bit is set, writes to this register will be discarded and this register will read as ...
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Status Register Name: SR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 CLKREADY • CLKREADY: Clock ready This bit is cleared when the ...
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Status Clear Register Name: SCR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 CLKREADY When the SR.BUSY bit is set, writes to this ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 CLKREADY Writing a zero to a bit in this register ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 CLKREADY Writing a zero to a bit in this register ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 CLKREADY The corresponding interrupt is disabled. 1: The corresponding ...
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Wake Enable Register Name: WER Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 When the SR.BUSY bit is set writes to this register ...
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Alarm Register Name: AR0/1 Access Type: Read/Write Offset: 0x20/0x24 Reset Value: 0x00000000 When the SR.BUSY bit is set writes to this register will be discarded and this register will read as ...
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Periodic Interval Register Name: PIR0/1 Access Type: Read/Write Offset: 0x30/0x34 Reset Value: 0x00000000 When the SR.BUSY bit is set writes to this register ...
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Clock Control Register Name: CLOCK Access Type: Read/Write Offset: 0x40 Reset Value: 0x00000000 When writing to this register, follow the sequence in • ...
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Digital Tuner Register Name: DTR Access Type: Read/Write Offset: 0x44 Reset Value: 0x00000000 When the SR.BUSY bit is set writes to this register will be ...
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Event Enable Register Name: EVE Access Type: Write-only Offset: 0x48 Reset Value: 0x00000000 When the SR.BUSY bit is set writes to this register ...
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Event Disable Register Name: EVD Access Type: Write-only Offset: 0x4C Reset Value: 0x00000000 When the SR.BUSY bit is set writes to this register ...
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Event Mask Register Name: EVM Access Type: Read-only Offset: 0x50 Reset Value: 0x00000000 The corresponding peripheral event is disabled. 1: The corresponding ...
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Calendar Value Name: CALV Access Type: Read/Write Offset: 0x54 Reset Value: 0x00000000 MONTH[1: HOUR[3: MIN[1:0] When the SR.BUSY bit is set writes to this register will be discarded and this register ...
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Parameter Register Name: PARAMETER Access Type: Read-only Offset: 0xF0 Reset Value PIR1WA PIR0WA This register gives the configuration used in the specific device. Also refer ...
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Version Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: 0x00000300 • VARIANT: Variant number • Reserved. No functionality associated. • VERSION: Version number ...
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Module configuration The specific configuration for each AST instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks according to the table in the System Bus Clock Connections section. ...
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Watchdog Timer (WDT) Rev: 4.1.0.0 10.1 Features • Watchdog Timer counter with 32-bit counter • Timing window watchdog • Clocked from system RC oscillator or the 32 KHz crystal oscillator • Configuration lock • WDT may be enabled at ...
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Power Management When the WDT is enabled, the WDT remains clocked in all sleep modes not possible to enter sleep modes where the source clock of CLK_CNT is stopped. Attempting will result in the ...
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To change the clock for the WDT the following steps need to be taken. Note that the WDT should always be disabled before changing the CLK_CNT source: 1. Write a zero to the Clock Enable (CEN) bit in the CTRL ...
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Figure 10-2. Basic Mode WDT Timing Diagram, normal operation rite the ...
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The PSEL and Time Ban Prescale Select (TBAN) fields in the CTRL Register selects the WDT timeout period T where T bit is not allowed. Doing so will result in a watchdog reset, the device will receive a reset and ...
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Disabling the WDT The WDT is disabled by writing a zero to the CTRL.EN bit. When disabling the WDT no other bits in the CTRL Register should be changed until the CTRL.EN bit reads back as zero. If the ...
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User Interface Table 10-1. WDT Register Memory Map Offset 0x000 Control Register 0x004 0x008 0x3FC Version Register Note: 1. The reset value for this register is device specific. Please refer to the Module Configuration section at the end of ...
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Control Register Name: CTRL Access Type: Read/Write Offset: 0x000 Reset Value: 0x00010080 FCD - • KEY This field must be written twice, first with key value 0x55, then ...
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DAR: WDT Disable After Reset 0: After a watchdog reset, the WDT will still be enabled. 1: After a watchdog reset, the WDT will be disabled. • EN: WDT Enable 0: WDT is disabled. 1: WDT is enabled. After ...
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Clear Register Name: CLR Access Type: Write-only Offset: 0x004 Reset Value: 0x00000000 When the Watchdog Timer is enabled, this Register must be periodically written within ...
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Status Register Name: SR Access Type: Read-only Offset: 0x008 Reset Value: 0x00000003 • CLEARED: WDT Counter Cleared This bit is cleared when writing ...
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Version Register Name: VERSION Access Type: Read-only Offset: 0x3FC Reset Value • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version ...
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Module Configuration The specific configuration for each WDT instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man- ager chapter for details. Table ...
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Interrupt Controller (INTC) Rev: 1.0.2.5 11.1 Features • Autovectored low latency interrupt service with programmable priority – 4 priority levels for regular, maskable interrupts – One Non-Maskable Interrupt • groups of interrupts with ...
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Figure 11-1. INTC Block Diagram NMIREQ IREQ63 IREQ34 IREQ33 IREQ32 IREQ31 IREQ2 IREQ1 IREQ0 11.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 11.4.1 Power Management If the ...
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Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, ...
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AT32UC3C 177 ...
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User Interface Table 11-1. INTC Register Memory Map Offset Register 0x000 Interrupt Priority Register 0 0x004 Interrupt Priority Register 1 ... 0x0FC Interrupt Priority Register 63 0x100 Interrupt Request Register 0 0x104 Interrupt Request Register 1 ... 0x1FC Interrupt ...
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Interrupt Priority Registers Name: IPR0...IPR63 Access Type: Read/Write Offset: 0x000 - 0x0FC Reset Value: 0x00000000 31 30 INTLEVEL[1: • INTLEVEL: Interrupt Level Indicates the EVBA-relative offset of the interrupt ...
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Interrupt Request Registers Name: IRR0...IRR63 Access Type: Read-only Offset: 0x0FF - 0x1FC Reset Value: N IRR[32*x+31] IRR[32*x+30] IRR[32*x+29 IRR[32*x+23] IRR[32*x+22] IRR[32*x+21 IRR[32*x+15] IRR[32*x+14] IRR[32*x+13 IRR[32*x+7] IRR[32*x+6] IRR[32*x+5] • IRR: Interrupt Request ...
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Interrupt Cause Registers Name: ICR0...ICR3 Access Type: Read-only Offset: 0x200 - 0x20C Reset Value: N • CAUSE: Interrupt Group Causing Interrupt of Priority ...
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Interrupt Request Signal Map The various modules may output Interrupt request signals. These signals are routed to the Inter- rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports groups of interrupt requests. Each ...
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Table 11-2. 32117C–AVR-08/11 Interrupt Request Signal Map 0 Control Area Network interface 1 Control Area Network interface 2 Control Area Network interface 3 Control Area Network interface 4 Control Area Network interface 9 5 Control Area Network interface 6 Control ...
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Table 11-2. 32117C–AVR-08/11 Interrupt Request Signal Map 0 General Purpose Input/Output Controller 1 General Purpose Input/Output Controller 2 General Purpose Input/Output Controller 3 General Purpose Input/Output Controller 4 General Purpose Input/Output Controller 5 General Purpose Input/Output Controller 6 General Purpose ...
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Table 11-2. 32117C–AVR-08/11 Interrupt Request Signal Map 0 Timer/Counter 34 1 Timer/Counter 2 Timer/Counter 0 Peripheral Event Controller 35 1 Peripheral Event Controller ADC controller interface with Touch 0 Screen functionality ADC controller interface with Touch 1 Screen functionality ADC ...
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Table 11-2. 32117C–AVR-08/11 Interrupt Request Signal Map 41 0 aWire 42 0 Ethernet MAC Universal Synchronous/Asynchronous 44 0 Receiver/Transmitter 45 0 Two-wire Master Interface 46 0 Two-wire Slave Interface AT32UC3C AW MACB USART4 TWIM2 TWIS2 186 ...
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External Interrupt Controller (EIC) Rev: 3.0.2.0 12.1 Features • Dedicated interrupt request for each interrupt • Individually maskable interrupts • Interrupt on rising or falling edge • Interrupt on high or low level • Asynchronous interrupts for sleep modes ...
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I/O Lines Description Table 12-1. Pin Name NMI EXTINTn 12.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 12.5.1 I/O Lines The external interrupt pins (EXTINTn and ...
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Each external interrupt INTn can be configured to produce an interrupt on rising or falling edge, or high or low level. External interrupts are configured by the MODE, EDGE, and LEVEL regis- ters. Each interrupt has a bit INTn in ...
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Figure 12-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on Figure 12-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on 12.6.3 Non-Maskable ...
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When CLK_SYNC is stopped only asynchronous interrupts remain active, and any short spike on this interrupt will wake up the device. EIC_WAKE will restart CLK_SYNC and ISR will be updated on the first rising edge of CLK_SYNC. Figure 12-4. Timing ...
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User Interface Table 12-2. EIC Register Memory Map Offset 0x000 Interrupt Enable Register 0x004 Interrupt Disable Register 0x008 Interrupt Mask Register 0x00C Interrupt Status Register 0x010 Interrupt Clear Register 0x014 0x018 0x01C 0x020 0x024 0x028 Asynchronous Register 0x030 0x034 ...
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Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x000 Reset Value: 0x00000000 INT30 23 22 INT23 INT22 15 14 INT15 INT14 7 6 INT7 INT6 • INTn: External Interrupt n Writing a zero to this ...
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Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x004 Reset Value: 0x00000000 INT30 23 22 INT23 INT22 15 14 INT15 INT14 7 6 INT7 INT6 • INTn: External Interrupt n Writing a zero to this ...
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Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x008 Reset Value: 0x00000000 INT30 23 22 INT23 INT22 15 14 INT15 INT14 7 6 INT7 INT6 • INTn: External Interrupt n 0: The corresponding interrupt is ...
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Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x00C Reset Value: 0x00000000 INT30 23 22 INT23 INT22 15 14 INT15 INT14 7 6 INT7 INT6 • INTn: External Interrupt interrupt event has ...
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Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x010 Reset Value: 0x00000000 INT30 23 22 INT23 INT22 15 14 INT15 INT14 7 6 INT7 INT6 • INTn: External Interrupt n Writing a zero to this ...
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Mode Register Name: MODE Access Type: Read/Write Offset: 0x014 Reset Value: 0x00000000 INT30 23 22 INT23 INT22 15 14 INT15 INT14 7 6 INT7 INT6 • INTn: External Interrupt n 0: The external interrupt is edge ...
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Edge Register Name: EDGE Access Type: Read/Write Offset: 0x018 Reset Value: 0x00000000 INT30 23 22 INT23 INT22 15 14 INT15 INT14 7 6 INT7 INT6 • INTn: External Interrupt n 0: The external interrupt triggers on ...
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Level Register Name: LEVEL Access Type: Read/Write Offset: 0x01C Reset Value: 0x00000000 INT30 23 22 INT23 INT22 15 14 INT15 INT14 7 6 INT7 INT6 • INTn: External Interrupt n 0: The external interrupt triggers on ...