AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 617

• Manufacturer Part Number: AT32UC3C0256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.6.12
25.6.12.1
Figure 25-51. Master Node with Peripheral DMA Controller (PDCM=1)
32117C–AVR-08/11
WRITE BUFFER
IDENTIFIER
CHKTYP
CHKDIS
PARDIS
FSDIS
DATA 0
DATA N
NACT
DLC
DLM
|
|
|
|
LIN Frame Handling With The Peripheral DMA Controller
Master Node Configuration
Peripheral DMA
Controller
The USART can be used in association with the Peripheral DMA Controller in order to transfer
data directly into/from the on- and off-chip memories without any processor intervention.
The Peripheral DMA Controller uses the trigger flags, TXRDY and RXRDY, to write or read into
the USART. The Peripheral DMA Controller always writes in the Transmit Holding register (THR)
and it always reads in the Receive Holding register (RHR). The size of the data written or read by
the Peripheral DMA Controller in the USART is always a byte.
The user can choose between two Peripheral DMA Controller modes by the PDCM bit in the LIN
Mode register (LINMR):
The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response
(NACT = PUBLISH).
The READ buffer contains the DATA if the USART receives the response (NACT =
SUBSCRIBE).
• PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the
• PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by
Peripheral DMA Controller in the Transmit Holding register THR (instead of the LIN Mode
register LINMR). Because the Peripheral DMA Controller transfer size is limited to a byte, the
transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS,
CHKTYP, DLM and FSDIS are written. During the second access the 8-bit DLC field is
written.
the user in the LIN Mode register (LINMR).
Peripheral
RXRDY
bus
NODE ACTION = PUBLISH
CONTROLLER
USART LIN
READ BUFFER
IDENTIFIER
WRITE BUFFER
CHKTYP
PARDIS
CHKDIS
FSDIS
NACT
DATA N
DATA 0
DLM
DLC
|
|
|
|
Peripheral DMA
Controller
Peripheral
RXRDY
TXRDY
bus
AT32UC3C
NODE ACTION = SUBSCRIBE
CONTROLLER
USART LIN
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