AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 806

• Manufacturer Part Number: AT32UC3C0256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.6.5
30.6.6
32117C–AVR-08/11
TDM Reception and Transmission Sequence
Serial Clock and Word Select Generation
In Time Division Multiplexed (TDM) format, 1 to 8 data words are sent or received within each
frame, As in the I
transmitted first, starting one clock period after the transition on the Word Select line. Each time
slot is 32-bit long.
Figure 30-3. TDM Reception and Transmission Sequence
Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the
Serial Clock. The IWS pin provides a frame synchronization signal, starting one ISCK period
before the MSB of channel 0.
The Time Division Multiplexed (TDM) format is selected by writing a one to the MR.FORMAT
field.
The Frame Sync pulse can be either one ISCK period or one 32-bit time slot. This selection is
done by writing the MR.TDMFS bit.
The number of channels is selected by writing the MR.CHANNELS field.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing
the MR.DATALENGTH field.
If the time slot allows for more data bits than programmed in the MR.DATALENGTH field, zeroes
are appended to the transmitted data word or extra received bits are discarded. If the time slot
allows for less data bits than programmed, the extra bits to be transmitted are not sent or the
missing bits are set to zero in the right-adjusted received data word.
The generation of clocks in the IISC is described in
In Slave mode, the Serial Clock and Word Select Clock are driven by an external master. ISCK
and IWS pins are inputs and no generic clock is required by the IISC.
In Master mode, the user can configure the Master Clock, Serial Clock, and Word Select Clock
through the Mode Register (MR). IMCK, ISCK, and IWS pins are outputs and a generic clock is
used to derive the IISC clocks.
Audio codecs connected to the IISC pins may require a Master Clock signal with a frequency
multiple of the audio sample frequency (fs), such as 256fs. When the IISC is in Master mode,
writing a one to MR.IMCKMODE will output GCLK_IISC as Master Clock to the IMCK pin, and
will divide GCLK_IISC to create the internal bit clock, output on the ISCK pin. The clock division
factor is defined by writing to MR.IMCKFS and MR.DATALENGTH, as described
Master Clock to fs Ratio” on page
Serial Clock (ISCK)
Frame sync (IWS)
Data (ISDI/ISDO)
2
S protocol, data bits are left-adjusted in the channel time slot, with the MSB
MSB
Channel 0
LSB
814.
MSB
Channel 1
LSB
Figure 30-4 on page
MSB
Channel 2
LSB
808.
AT32UC3C
MSB
Channel 3
LSB
”IMCKFS:
806