AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 489

• Manufacturer Part Number: AT32UC3C0256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.4.4
24.4.5
24.5
24.5.1
32117C–AVR-08/11
Functional Description
Interrupt
Debug Operation
Memory Interface
ager. It is recommended to disable the MACB before disabling the clocks, to avoid freezing the
MACB in an undefined state.
The synchronization module in the MACB requires that the bus clock (CLK_MACB_HSB) runs
on at least the speed of the macb_tx/RX_CLK, which is 25MHz in 100Mbps, and 2.5MHZ in
10Mbps in MII mode and 50MHz in 100Mbps, and 5MHZ in 10Mbps in RMII mode.
The MACB interrupt request line is connected to the interrupt controller. Using the MACB inter-
rupt requires the interrupt controller to be programmed first.
When an external debugger forces the CPU into debug mode, the MACB continues normal
operation. If the MACB is configured in a way that requires it to be periodically serviced by the
CPU through interrupts or similar, improper operation or data loss may result during debugging.
The control registers drive the MDIO interface, setup DMA activity, start frame transmission and
select modes of operation such as full or half-duplex.
The receive sub-module checks for valid preamble, Frame Check Sequence (FCS), alignment
and length, and presents received frames to the address checking sub-module and DMA
interface.
The transmit sub-module takes data from the DMA interface, adds preamble and, if necessary,
pad and FCS, and transmits data according to the Carrier Sense Multiple Access with Collision
Detect (CSMA/CD) protocol. The start of transmission is deferred if Carrier Sense (CRS) is
active.
If Collision (COL) becomes active during transmission, a jam sequence is asserted and the
transmission is retried after a random back off. CRS and COL have no effect in full duplex mode.
The DMA interface can access external memory through its High Speed Bus (HSB). It contains
receive and transmit FIFOs for buffering frame data. It loads the transmit FIFO and empties the
receive FIFO using HSB bus master operations. Received data is not sent to memory until the
address checking logic has determined that the frame should be copied. Received or transmit-
ted frames are stored in one or more buffers. Receive buffers have a fixed length of 128 bytes.
Transmit buffers range in length between 0 and 2047 bytes, and up to 128 buffers are allowed
per frame. The DMA interface manages the transmit and receive frame buffer queues. These
queues can hold multiple frames.
Frame data is transferred to and from the MACB by the DMA interface. All transfers are 32-bit
words and may be single accesses or bursts of 2, 3 or 4 words. Burst accesses do not cross six-
teen-byte boundaries. Bursts of 4 words are the default data transfer; single accesses or bursts
of less than four words may be used to transfer data at the beginning or the end of a buffer.
The DMA interface performs six types of operation on the bus. In order of priority, these are:
1. Receive buffer manager write
2. Receive buffer manager read
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