AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 992

• Manufacturer Part Number: AT32UC3C0256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C0256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 123
• Ext Interrupts: 144
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 20
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.6.5.7
32117C–AVR-08/11
Write Protect Registers
To prevent any single software error that may corrupt PWM behavior, the registers listed below
can be write-protected by writing the WPCMD field in the
page 1027
There are two types of Write Protect:
Both Write Protect can be applied independently to a particular register group thanks to the
WPCMD and WPRG fields in WPCR register. If at least one of the Write Protect is active, the
register group is write-protected. The WPCMD field allows to perform the following actions
depending on its value:
At any time, the user can know which Write Protect is active in which register group by the
WPSWS and WPHWS fields in the
If a write access in a write-protected register is detected, then the WPVS bit in the WPSR regis-
ter is set and the WPVSRC field indicates in which register the write access has been attempted,
through its address offset without the two LSBs.
The WPVS and WPSR fields are automatically reset after reading the WPSR register.
• Register group 0:
• Register group 1:
• Register group 2:
• Register group 3:
• Register group 4:
• Register group 5:
• the Write Protect SW, which can be enabled or disabled.
• the Write Protect HW, which can just be enabled, only a hardware reset of the PWM
• 0: Disabling the Write Protect SW of the register groups of which the WPRG bit is at 1.
• 1: Enabling the Write Protect SW of the register groups of which the WPRG bit is at 1.
• 2: Enabling the Write Protect HW of the register groups of which the WPRG bit is at 1.
controller can disable it.
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–
–
–
–
–
–
–
–
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”Clock Register” on page 996
”Disable Register” on page 999
”Sync Channels Mode Register” on page 1005
”Channel Mode Register” on page 1035
”Stepper Motor Mode Register” on page 1026
”Channel Period Register” on page 1039
”Channel Period Update Register” on page 1041
”Channel Dead Time Register” on page 1044
”Channel Dead Time Update Register” on page 1045
”Fault Mode Register” on page 1020
”Fault Protection Value Register” on page 1023
(WPCR). They are divided into 6 groups:
”Write Protect Status Register” on page 1029
”Write Protect Control Register” on
AT32UC3C
(WPSR).
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