AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 309

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AT32UC3C0256C

Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C0256C

Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Quantity
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Part Number:
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Manufacturer:
Atmel
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10 000
Part Number:
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Figure 18-3.
18.6.3
18.6.3.1
18.6.3.2
32117C–AVR-08/11
Connection to External Devices
SMC
Data bus width
Byte write or byte select access
Memory Connections for Six External Devices
NCS[0] - NCS[5]
A[AD_MSB:0]
D[15:0]
NWE
NRD
A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by
the Data Bus Width field in the Mode Register (MODE.DBW) for the corresponding chip select.
Figure 18-4 on page 309
page 310
Each chip select with a 16-bit data bus can operate with one of two different types of write
access: byte write or byte select access. This is controlled by the Byte Access Type bit in the
MODE register (MODE.BAT) for the corresponding chip select.
Figure 18-4.
shows how to connect a 512K x 16-bit memory on NCS2.
Memory Connection for an 8-bit Data Bus
SMC
shows how to connect a 512K x 8-bit memory on NCS2.
NCS[2]
A[18:2]
D[7:0]
NWE
NRD
A0
A1
8 or 16
NCS0
NCS1
NCS2
A[AD_MSB:0]
D[15:0] or D[7:0]
Memory Enable
Output Enable
Write Enable
NCS3
Memory Enable
NCS4
Memory Enable
NCS5
Memory Enable
D[7:0]
A[18:2]
Write Enable
Output Enable
Memory Enable
A0
A1
Memory Enable
Memory Enable
AT32UC3C
Figure 18-5 on
309

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