AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 501
AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
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Table 24-5.
24.5.17.1
32117C–AVR-08/11
Pin Name
TX_CLK
CRS
COL
RX_DV
RXD[3:0]
RX_ER
RX_CLK
TX_EN
TXD[3:0]
TX_ER
RMII Transmit and Receive Operation
Pin Configuration
Transmit Clock
Carrier Sense
Collision Detect
Data Valid
RXS[3:0] 4-bit Receive Data
Receive Error
Receive Clock
Transmit Enable
TXD[3:0] 4-bit Transmit Data
Transmit Error
The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in
the IEEE 802.3u standard. The signals used by the MII and RMII interfaces are described in
Table
The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII. It
uses 2 bits for transmission (TXD[1:0]) and two bits for reception (RXD[1:0]). There are Transmit
Enable (TX_EN), a Receive Error (RX_ER), a Carrier Sense (CRS), and a 50 MHz Reference
Clock (TX_CLK) for 100Mb/s data rate.
The same signals are used internally for both the RMII and the MII operations. The RMII maps
these signals in a more pin-efficient manner. The transmit and receive bits are converted from a
4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. The carrier sense
and data valid signals are combined into the RX_DV signal. This signal contains information on
carrier sense, FIFO status, and validity of the data. Transmit error bit (TX_ER) and collision
detect (COL) are not used in RMII mode.
24-5.
MII
Reference Clock
Carrier Sense/Data Valid
RXD[1:0] 2-bit Receive Data
Receive Error
Transmit Enable
TXD[1:0] 2-bit Transmit Data
RMII
AT32UC3C
501
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