AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 1107
AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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36.6.4.3
36.6.4.4
32117C–AVR-08/11
Dual-sequencer mode (simultaneous sampling)
Sequencer behavior on a Start Of Conversion
Figure 36-2. Single Sequencer Chronogram (assuming SRES=8, SHD=0)
The ADC has the ability to sample two pairs of ADCINx inputs simultaneously (see
provided that one pair is from the inputs available on the sequencer 0 and the other is from the
inputs available on the sequencer 1 (see
pling mode, the SSMQ bit needs to be set in the CFG register.
Figure 36-3. Dual Sequencer Chronogram (assuming SRES=8, SHD=0)
In this chronogram, ADCCONV signal represents the value being sampled by the ADC
Thanks to the SOCB bit in the SEQCFGx register, 2 different sequencer behaviors are possible:
Table 36-5.
SOCB
0
1
Comment
All sequence conversions are performed on a SOC event.
A single conversion belonging to the sequence is performed on a SOC event.
SOCB Behavior
Figure
36-1). To put the ADC into simultaneous sam-
AT32UC3C
Figure
36-3),
1107
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