AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 1050
AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
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- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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34.6.1.2
34.6.1.3
32117C–AVR-08/11
Trigger
Quadrature decoder logic and digital filter
{A,B} =
QEPA
QEPB
(0,0)
Figure 34-3. Clock Control
A trigger resets the QDEC counter and starts CLK_QDEC_INT. Two triggers are possible:
•
•
The QDEC counter is reset when the peripheral trigger event occurs.
The quadrature decoder logic converts the 2-phase signals QEPA and QEPB in a count pulse
signal (QPulse) for each transition and a DIR signal to indicate the rotation direction.
Figure 34-4. Quadrature Description
The QEPI signal may be used to detect a reference position once per revolution.
The 3 inputs (QEPA/QEPB/QEPI) can be inverted by writing to appropriate bits in CF.
(0,1)
A software trigger, by writing a one to the Software Trigger bit in CTRL
(CTRL.SWTRG).
Trigger peripheral event from the PEVC: If enabled by writing a one to the Event
Trigger Enable bit in the Configuration Register (CF.EVTRGE).
PEVC trigger
CTRL[CLKEN]= 1
(1,1)
(1,0)
CTRL[CLKEN]=0
A
N
D
Increment
Increment
counter
GCLK_QDEC
counter
Decrement
00
Reset
Set
Decrement
counter
counter
Q
SR[CLKEN]
10
01
A
N
D
Decrement
Decrement
counter
counter
CLK_QDEC_INT
11
AT32UC3C
Increment
counter
Increment
counter
1050
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