AT32UC3C0256C Atmel Corporation, AT32UC3C0256C Datasheet - Page 762
AT32UC3C0256C
Manufacturer Part Number
AT32UC3C0256C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C0256C
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
123
Ext Interrupts
144
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
20
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
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Price
- AT32UC3A0128 PDF datasheet
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- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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29.3
29.4
29.5
29.5.1
29.5.2
29.5.3
29.5.4
32117C–AVR-08/11
Block Diagram
I/O Lines Description
Product Dependencies
I/O Lines
Power Management
Clocks
Memory
Figure 29-1. CANIF Block Diagram
Table 29-1.
In order to use this module, other parts of the system must be configured correctly, as described
below.
CANIF pins are multiplexed with other peripherals. User must first program the I/O Controller to
give control of the pins to the CANIF.
If the CPU enters a sleep mode that disables clocks used by CANIF, it will stop functioning and
resume operation after the system wakes up from sleep mode.
CANIF is connected to both the HSB and the PB, and therefore uses a HSB clock
(CLK_CANIF_HSB) and a PB clock (CLK_CANIF_PB). These clocks are generated by the
Power Manager. These clocks are enabled at reset, and can be disabled in the Power Manager.
CANIF uses a GCLK as clock source (CAN clock) for the CAN bus communication
(GCLK_CANIF). User must make sure this clock is running and frequency is correct before any
operation.
Messages can be stored in CPU or HSB RAM, so user must allocate RAM space for CAN
messages.
TXLINE(n)
RXLINE(n)
Pin Name
RAM
I/O Lines Description
Transmission line of channel n
Reception line of channel n
HSB
Pin Description
PB
Msg Handling
& Filtering
Output
Type
Input
CANIF
Protocol
Engine
clock
CAN
AT32UC3C
TXLINE(0)
RXLINE(0)
RXLINE(n)
TXLINE(n)
.
.
.
762
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