AT89C5130A-M Atmel Corporation, AT89C5130A-M Datasheet - Page 93
AT89C5130A-M
Manufacturer Part Number
AT89C5130A-M
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C5130A-M.pdf
(188 pages)
2.AT89C5130A-M.pdf
(4 pages)
3.AT89C5130A-M.pdf
(34 pages)
Specifications of AT89C5130A-M
Flash (kbytes)
16 Kbytes
Max. Operating Frequency
48 MHz
Cpu
8051-12C
Max I/o Pins
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
1.25
Eeprom (bytes)
1024
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART/USB
Watchdog
Yes
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19. Serial Peripheral Interface (SPI)
19.1
19.2
19.2.1
19.2.2
4337K–USB–04/08
Features
Signal Description
Master Output Slave Input (MOSI)
Master Input Slave Output (MISO)
The Serial Peripheral Interface module (SPI) allows full-duplex, synchronous, serial communica-
tion between the MCU and peripheral devices, including other MCUs.
Features of the SPI module include the following:
Figure 19-1
peripherals. The bus is made of three wires connecting all the devices:
Figure 19-1. SPI Master/Slaves Interconnection
The Master device selects the individual Slave devices by using four pins of a parallel port to
control the four SS pins of the Slave devices.
This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI
line is used to transfer data in series from the Master to the Slave. Therefore, it is an output sig-
nal from the Master, and an input signal to a Slave. A byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO
line is used to transfer data in series from the Slave to the Master. Therefore, it is an output sig-
nal from the Slave, and an input signal to the Master. A byte (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
• Full-duplex, three-wire synchronous transfers
• Master or Slave operation
• Eight programmable Master clock rates
• Serial clock with programmable polarity and phase
• Master mode fault error flag with MCU interrupt capability
• Write collision flag protection
shows a typical SPI bus configuration using one Master controller and many Slave
Master
Slave 4
MISO
MOSI
SCK
SS
0
1
2
3
VDD
Slave 3
AT89C5130A/31A-M
Slave 1
Slave 2
93
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