ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 140
ATmega1284PR231
Manufacturer Part Number
ATmega1284PR231
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT86RF231.pdf
(198 pages)
2.ATMEGA1284PR231.pdf
(380 pages)
3.ATMEGA1284PR231.pdf
(20 pages)
Specifications of ATmega1284PR231
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
16
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
2
Antenna Diversity
Yes
External Pa Control
Yes
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
13.2
Transmit Current Consumption (ma)
14.4
Link Budget (dbm)
104
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15. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
15.1
15.2
8059D–AVR–11/09
Features
Overview
•
•
•
•
•
•
•
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-12.. For the actual
placement of I/O pins, see
ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
are listed in the
The Power Reduction Timer/Counter2 bit, PRTIM2, in
page 46
Figure 15-1. 8-bit Timer/Counter Block Diagram
Single Channel Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock
must be written to zero to enable Timer/Counter2 module.
Status flags
”Register Description” on page
Timer/Counter
TCCRnA
OCRnA
TCNTn
OCRnB
=
=
”Pin Configurations” on page
Direction
Count
ASSRn
Clear
Synchronized Status flags
Control Logic
TOP
=
TCCRnB
asynchronous mode
Value
BOTTOM
Fixed
TOP
select (ASn)
clk
=
Tn
0
153.
Prescaler
Synchronization Unit
”PRR0 – Power Reduction Register 0” on
OCnA
(Int.Req.)
OCnB
(Int.Req.)
Generation
Generation
2. CPU accessible I/O Registers, includ-
Waveform
Waveform
ATmega1284P
TOVn
(Int.Req.)
OCnA
OCnB
Oscillator
T/C
clk
I/O
clk
clk
I/O
ASY
TOSC1
TOSC2
140
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