ATmega1284PR231 Atmel Corporation, ATmega1284PR231 Datasheet - Page 330
ATmega1284PR231
Manufacturer Part Number
ATmega1284PR231
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT86RF231.pdf
(198 pages)
2.ATMEGA1284PR231.pdf
(380 pages)
3.ATMEGA1284PR231.pdf
(20 pages)
Specifications of ATmega1284PR231
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
20 MHz
Max I/o Pins
32
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
16
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
3
Frequency Band
2.4 GHz
Max Data Rate (mb/s)
2
Antenna Diversity
Yes
External Pa Control
Yes
Power Output (dbm)
3
Receiver Sensitivity (dbm)
-101
Receive Current Consumption (ma)
13.2
Transmit Current Consumption (ma)
14.4
Link Budget (dbm)
104
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Table 26-7.
Notes:
8059D–AVR–11/09
Symbol
t
t
t
t
t
t
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
1. In ATmega1284P, this parameter is characterized and not 100% tested.
2. Required only for f
3. Cb = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
5. This requirement applies to all ATmega1284P Two-wire Serial Interface operation. Other devices connected to the Two-wire
6. The actual low period generated by the ATmega1284P Two-wire Serial Interface is (1/f
7. The actual low period generated by the Two-wire Serial Interface is (1/f
Serial Bus need only obey the general f
than 6 MHz for the low time requirement to be strictly met at f
strictly met for f
speed (400 kHz) with other ATmega1284P devices, as well as any other device with a proper t
Parameter
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START
condition
2-wire Serial Bus Requirements (Continued)
SCL
Figure 26-5. 2-wire Serial Bus Timing
SCL
> 308 kHz when f
> 100 kHz.
SCL
SDA
t
SU;STA
CK
= 8 MHz. Still, ATmega1284P devices connected to the bus may communicate at full
SCL
requirement.
t
HD;STA
t
t
of
LOW
f
f
f
f
f
f
f
f
f
f
f
f
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
Condition
t
HIGH
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
≤ 100 kHz
> 100 kHz
SCL
t
HD;DAT
= 100 kHz.
SCL
t
LOW
- 2/f
CK
t
SU;DAT
), thus the low time requirement will not be
SCL
250
100
Min
4.0
0.6
4.7
0.6
4.0
0.6
4.7
1.3
0
0
- 2/f
ATmega1284P
CK
LOW
), thus f
acceptance margin.
t
SU;STO
CK
t
r
3.45
Max
0.9
–
–
–
–
–
–
–
–
–
–
must be greater
t
BUF
Units
µs
µs
µs
µs
µs
µs
ns
ns
µs
µs
µs
µs
330
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