ATmega168 Atmel Corporation, ATmega168 Datasheet - Page 267
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATmega168
Manufacturer Part Number
ATmega168
Description
Manufacturer
Atmel Corporation
Specifications of ATmega168
Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA168
Manufacturer:
AVAILINK
Quantity:
1 590
Company:
Part Number:
ATmega168-15AD
Manufacturer:
VISHAY
Quantity:
15 600
Part Number:
ATmega168-15AT1
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega168-15MT
Manufacturer:
ATMEL
Quantity:
686
Part Number:
ATmega168-15MT
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega168-15MT1
Manufacturer:
ATMEL
Quantity:
372
Part Number:
ATmega168-15MZ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega168-20AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
26.3
26.3.1
2545T–AVR–05/11
Register description
SPMCSR – Store program memory control and status register
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Program memory operations.
• Bit 7 – SPMIE: SPM interrupt enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SELF-
PRGEN bit in the SPMCSR Register is cleared. The interrupt will not be generated during
EEPROM write or SPM.
• Bit 6 – RWWSB: Read-while-write section busy
This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero
in Atmel ATmega48.
• Bit 5 – Res: Reserved bit
This bit is a reserved bit in the Atmel ATmega48/88/168 and will always read as zero.
• Bit 4 – RWWSRE: Read-while-write section read enable
The functionality of this bit in ATmega48 is a subset of the functionality in ATmega88/168. If the
RWWSRE bit is written while filling the temporary page buffer, the temporary page buffer will be
cleared and the data will be lost.
• Bit 3 – BLBSET: Boot lock bit set
The functionality of this bit in ATmega48 is a subset of the functionality in ATmega88/168. An
LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR
Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. See
• Bit 2 – PGWRT: Page write
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed
within four clock cycles. The CPU is halted during the entire Page Write operation.
Bit
0x37 (0x57)
Read/write
Initial value
Wait_ee:
sbic EECR, EEPE
rjmp Wait_ee
; SPM timed sequence
out
spm
; restore SREG (to enable interrupts if originally enabled)
out
ret
SPMCSR, spmcrval
SREG, temp2
SPMIE
R/W
7
0
RWWSB
R
“Reading the fuse and lock bits from software” on page 264
6
0
R
5
–
0
RWWSRE
R/W
4
0
BLBSET
R/W
3
0
PGWRT
R/W
2
0
ATmega48/88/168
PGERS
R/W
1
0
SELFPRGEN
R/W
0
0
for details.
SPMCSR
267