ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 169
ATmega406
Manufacturer Part Number
ATmega406
Description
Manufacturer
Atmel Corporation
Specifications of ATmega406
Flash (kbytes)
40 Kbytes
Pin Count
48
Max. Operating Frequency
1 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
18
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
1.9
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-30 to 85
I/o Supply Class
4.0 to 25
Operating Voltage (vcc)
4.0 to 25
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Pwm Channels
2
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega406-1AAU
Manufacturer:
AT
Quantity:
20 000
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25.10 Bus Connect/Disconnect for Two-wire Serial Interface
25.10.1
2548E–AVR–07/06
TWBCSR – TWI Bus Control and Status Register
The Bus Connect/Disconnect module is an addition to the TWI Interface. Based on a configura-
tion bit, an interrupt can be generated either when the TWI bus is connected or disconnected.
Figure 25-23
data and clock lines, respectively.
When the TWI bus is connected, both the SDA and the SCL lines will become high simulta-
neously. If the TWBCIP bit is cleared, the interrupt will be executed if enabled. Once the bus is
connected, the TWBCIP bit should be set. This enables detection of when the bus is discon-
nected, and prevents repetitive interrupts every time both the SDA and SCL lines are high (e.g.
bus IDLE state).
When the TWI bus is disconnected, both the SDA and the SCL lines will become low simulta-
neously. If the TWBCIP bit is set, the interrupt will be executed if enabled and if both lines
remain low for a configurable time period. By adding this time constraint, unwanted interrupts
caused by both lines going low during normal bus communication is prevented.
Figure 25-23. Overview of Bus Connect/Disconnect.
• Bit 7 - TWBCIF: TWI Bus Connect/Disconnect Interrupt Flag
Based on the TWBCIP bit, the TWBCIF bit is set when the TWI bus is connected or discon-
nected. TWBCIF is cleared by hardware when executing the corresponding interrupt handling
vector. Alternatively, TWBCIF is cleared by writing a logic one to the flag. When the SREG I-bit,
TWBCIE (TWI Bus Connect/Disconnect Interrupt Enable), and TWBCIF are set, the TWI Bus
Bit
(0xBE)
Read/Write
Initial Value
SDA
SCL
TWBCIF
illustrates the Bus Connect/Disconnect logic, where SDA and SCL are the TWI
R/W
7
X
TWBCIE
R/W
6
0
5
–
R
0
R
4
–
0
TWBCIP
START
R
3
–
0
DELAY ELEMENT
TWBDT1
8-BIT DATA BUS
TWBCSR
R/W
2
0
DELAY
TWBDT0
OUTPUT
R/W
1
0
SET TWBCIF
TWBCIP
R/W
0
0
ATmega406
TWBCSR
IRQ
169
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