ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 31

• Manufacturer Part Number: ATmega406
• Manufacturer: Atmel Corporation

Specifications of ATmega406

• Flash (kbytes): 40 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 1 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 18
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -30 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Pwm Channels: 2
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8. Power Management and Sleep Modes
8.0.1
2548E–AVR–07/06
SMCR – Sleep Mode Control Register
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2:0 bits in the SMCR Register select which sleep
mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Power-off) will be activated by
the SLEEP instruction. See
MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition
to the start-up time, executes the interrupt routine, and resumes execution from the instruction
following SLEEP. The contents of the register file and SRAM are unaltered when the device
wakes up from any sleep mode except Power-off. If a reset occurs during sleep mode, the MCU
wakes up and executes from the Reset Vector. The MCU will reset when returning from Power-
off mode.
Figure 7-1 on page 25
bution. The figure is helpful in selecting an appropriate sleep mode.
The Sleep Mode Control Register contains control bits for power management.
• Bits 7:4 – Res: Reserved Bits
These bits are reserved bits in the ATmega406, and will always read as zero.
• Bits 3:1 – SM2:0: Sleep Mode Select Bits 2, 1 and 0
These bits select between the five available sleep modes as shown in
Table 8-1.
Note:
Bit
0x33 (0x53)
Read/Write
Initial Value
SM2
1. SMCR is auto-cleared after 4 cycles when this value is set and the SE bit is written to logic
0
0
0
0
1
1
1
1
one. To enter this mode, execute SLEEP instruction within 4 cycles after writing SE to logic
one.
Sleep Mode Select
R
7
–
0
presents the different clock systems in the ATmega406, and their distri-
SM1
R
6
–
0
0
0
1
1
0
0
1
1
Table 8-1
R
5
–
0
for a summary. If an enabled interrupt occurs while the
SM0
R
4
–
0
0
1
0
1
0
1
0
1
SM2
R/W
3
0
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Power-save
Power-off
Reserved
Reserved
Reserved
SM1
R/W
2
0
(1)
SM0
R/W
Table
1
0
ATmega406
8-1.
R/W
SE
0
0
SMCR
31