ATmega406 Atmel Corporation, ATmega406 Datasheet - Page 57
ATmega406
Manufacturer Part Number
ATmega406
Description
Manufacturer
Atmel Corporation
Specifications of ATmega406
Flash (kbytes)
40 Kbytes
Pin Count
48
Max. Operating Frequency
1 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
18
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
1.9
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-30 to 85
I/o Supply Class
4.0 to 25
Operating Voltage (vcc)
4.0 to 25
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Pwm Channels
2
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega406-1AAU
Manufacturer:
AT
Quantity:
20 000
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12.2.2
12.2.3
2548E–AVR–07/06
EIMSK – External Interrupt Mask Register
EIFR – External Interrupt Flag Register
Table 12-1.
Note:
Table 12-2.
• Bits 7:4 – RES: Reserved Bits
These bits are reserved bits ins the ATmega406, and will always read as zero.
• Bits 3:0 – INT3 - INT0: External Interrupt Request 3 - 0 Enable
When an INT3 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the
External Interrupt Control Register – EICRA – defines whether the external interrupt is activated
on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt
request even if the pin is enabled as an output. This provides a way of generating a software
interrupt.
• Bits 7:4 – RES: Reserved Bits
These bits are reserved bits ins the ATmega406, and will always read as zero.
• Bits 3:0 – INTF3 - INTF0: External Interrupt Flags 3 - 0
When an edge or logic change on the INT3:0 pin triggers an interrupt request, INTF3:0 becomes
set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT3:0 in EIMSK, are
Bit
0x1D (0x3D)
Read/Write
Initial Value
Bit
0x1C (0x3C)
Read/Write
Initial Value
Symbol
ISCn1
t
INT
0
0
1
1
1. n = 3, 2, 1, or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Parameter
Minimum pulse width for asynchronous
external interrupt
Interrupt Sense Control
Asynchronous External Interrupt Characteristics
ISCn0
R
R
7
–
0
7
–
0
0
1
0
1
Description
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request.
The falling edge of INTn generates an interrupt request.
The rising edge of INTn generates an interrupt request.
R
R
6
–
0
6
–
0
R
R
5
–
0
5
–
0
(1)
R
R
4
–
0
4
–
0
INTF3
INT3
R/W
R/W
Condition
3
0
3
0
INTF2
INT2
R/W
R/W
2
0
2
0
Min
INTF1
INT1
R/W
R/W
1
0
1
0
ATmega406
Typ
50
INTF0
INT0
R/W
R/W
0
0
0
0
Max
EIMSK
Units
EIFR
ns
57
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