ATmega8535 Atmel Corporation, ATmega8535 Datasheet - Page 120

• Manufacturer Part Number: ATmega8535
• Manufacturer: Atmel Corporation

Specifications of ATmega8535

• Flash (kbytes): 8 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Force Output Compare
Compare Match Blocking by
TCNT2 Write
Using the Output Compare
Unit
120
ATmega8535(L)
Figure 55. Output Compare Unit, Block Diagram
The OCR2 Register is double buffered when using any of the pulse width modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,
the double buffering is disabled. The double buffering synchronizes the update of the
OCR2 Compare Register to either top or bottom of the counting sequence. The synchro-
nization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR2 Register access may seem complex, but this is not the case. When the dou-
ble buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double
buffering is disabled the CPU will access the OCR2 directly.
In non-PWM waveform generation modes, the match output of the comparator can be
forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare
Match will not set the OCF2 Flag or reload/clear the timer, but the OC2 pin will be
updated as if a real Compare Match had occurred (the COM21:0 bits settings define
whether the OC2 pin is set, cleared or toggled).
All CPU write operations to the TCNT2 Register will block any Compare Match that
occurs in the next timer clock cycle, even when the timer is stopped. This feature allows
OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when
the Timer/Counter clock is enabled.
Since writing TCNT2 in any mode of operation will block all compare matches for one
timer clock cycle, there are risks involved when changing TCNT2 when using the output
compare channel, independently of whether the Timer/Counter is running or not. If the
value written to TCNT2 equals the OCR2 value, the Compare Match will be missed,
resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value
equal to BOTTOM when the counter is down-counting.
The setup of the OC2 should be performed before setting the Data Direction Register for
the port pin to output. The easiest way of setting the OC2 value is to use the force output
compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even
when changing between Waveform Generation modes.
bottom
FOCn
top
OCRn
Waveform Generator
WGMn1:0
=
(8-bit Comparator )
DATA BUS
COMn1:0
TCNTn
OCFn (Int.Req.)
OCxy
2502K–AVR–10/06