ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 112

• Manufacturer Part Number: ATtiny48
• Manufacturer: Atmel Corporation

Specifications of ATtiny48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.11.2
112
ATtiny48/88
TCCR1B – Timer/Counter1 Control Register B
Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear
Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM)
modes.
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the
Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM1[3:0] bits located in the
TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCR1B is written.
• Bits 4:3 – WGM1[3:2]: Waveform Generation Mode
See TCCR1A Register description.
• Bits 2:0 – CS1[2:0]: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
12-10
Table 12-6.
Bit
(0x81)
Read/Write
Initial Value
CS12
0
0
0
0
1
and
(See “Modes of Operation” on page
Figure
CS11
0
0
1
1
0
Clock Select Bit Description
ICNC1
R/W
7
0
12-11.
CS10
ICES1
0
1
0
1
0
R/W
6
0
Description
No clock source (Timer/Counter stopped).
clk
clk
clk
clk
I/O
I/O
I/O
I/O
R
5
–
0
/1 (No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
WGM13
R/W
100.).
4
0
WGM12
R/W
3
0
CS12
R/W
2
0
CS11
R/W
1
0
CS10
R/W
0
0
8008H–AVR–04/11
TCCR1B
Figure