ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 85

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ATtiny48

Manufacturer Part Number
ATtiny48
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATtiny48

Flash (kbytes)
4 Kbytes
Pin Count
32
Max. Operating Frequency
12 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes

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11.8
11.8.1
8008H–AVR–04/11
8-bit Timer/Counter Register Description
TCCR0A – Timer/Counter Control Register A
Figure 11-7. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
Figure 11-8
is TOP.
Figure 11-8. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 3 – CTC0: Clear Timer on Compare Match Mode
This bit control the counting sequence of the counter, the source for maximum (TOP) counter
value, see
mode (counter), Clear Timer on Compare Match (CTC) mode (see
page
Bit
0x25 (0x45)
Read/Write
Initial Value
TCNTn
TCNTn
(clk
(clk
OCRnx
OCRnx
83).
OCFnx
(CTC)
OCFnx
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/8)
/8)
Table
shows the setting of OCF0A and the clearing of TCNT0 in CTC mode where OCR0A
caler (f
7
R
0
11-2. Modes of operation supported by the Timer/Counter unit are: Normal
clk_I/O
OCRnx - 1
TOP - 1
/8)
R
6
0
R
5
0
OCRnx
TOP
R
4
0
OCRnx Value
TOP
CTC0
R/W
3
0
OCRnx + 1
BOTTOM
CS02
R/W
2
0
“Modes of Operation” on
CS01
R/W
1
0
ATtiny48/88
BOTTOM + 1
CS00
OCRnx + 2
R/W
0
0
clk_I/O
/8)
TCCR0A
85

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