ATtiny48 Atmel Corporation, ATtiny48 Datasheet - Page 22

• Manufacturer Part Number: ATtiny48
• Manufacturer: Atmel Corporation

Specifications of ATtiny48

• Flash (kbytes): 4 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 12 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 28
• Ext Interrupts: 28
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5.3.5
22
ATtiny48/88
Preventing EEPROM Corruption
To write an EEPROM memory location follow the procedure below:
The EEPE bit remains set until the write operation has completed. While the device is busy with
programming, it is not possible to do any other EEPROM operations.
During periods of low V
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
At low supply voltages data in EEPROM can be corrupted in two ways:
EEPROM data corruption is avoided by keeping the device in reset during periods of insufficient
power supply voltage. This is easily done by enabling the internal Brown-Out Detector (BOD). If
BOD detection levels are not sufficient for the design, an external reset circuit for low V
used.
Provided that supply voltage is sufficient, an EEPROM write operation will be completed even
when a reset occurs.
• Poll the EEPROM Program Enable bit (EEPE) in EEPROM Control Register (EECR) to make
• Set mode of programming by writing EEPROM Programming Mode bits (EEPM0 and
• Write target address to EEPROM Address Registers (EEARH/EEARL).
• Write target data to EEPROM Data Register (EEDR).
• Enable write by setting EEPROM Master Program Enable (EEMPE) in EEPROM Control
• The supply voltage is too low to maintain proper operation of an otherwise legitimate
• The supply voltage is too low for the CPU and instructions may be executed incorrectly.
sure no other EEPROM operations are in process. If set, wait to clear.
EEPM1) in EEPROM Control Register (EECR). Alternatively, data can be written in one
operation or the write procedure can be split up in erase, only, and write, only.
Register (EECR). Within four clock cycles, start the write operation by setting the EEPROM
Program Enable bit (EEPE) in the EEPROM Control Register (EECR). During the write
operation, the CPU is halted for two clock cycles before executing the next instruction.
EEPROM program sequence.
CC
, the EEPROM data can be corrupted because the supply voltage is
8008H–AVR–04/11
CC
can be