ATxmega16A4U Atmel Corporation, ATxmega16A4U Datasheet - Page 332

• Manufacturer Part Number: ATxmega16A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega16A4U

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 3.3
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

27.3.1
27.3.2
27.3.3
8331A–AVR–07/11
Base Address
Address Size
Chip Select as Address Lines
The base address is the lowest address in the address space for a chip select. This decides the
first location in data memory space where the connected memory hardware can be accessed.
The base address associated with each chip select must be on a 4Kbyte boundary minimum.
Figure 27-1. Base Address
The address size selects how many bits of the address that should be compared when generat-
ing a chip select. The address size can be anything from 256bytes to 16Mbytes. If the address
space is set to anything larger than 4Kbytes, the base address must be on a boundary equal to
the address space. With 1M byte address space for a chip select, the base address must be on
a 0, 1Mbyte, 2Mbyte etc. boundary.
If the EBI is configured so that if the address spaces overlap, the internal memory space have
priority, followed by Chip Select 0 (CS0), CS1, CS2 and CS3.
If any Chip Select lines are unused, these can in some combinations be used as address lines .
This enables larger external memory or external CS generation. Each column in
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select lines (Ann). Column four shows that all four CS lines are used as address lines when only
CS3 is enabled.
Figure 27-2. Chip Select and address line combinations
shows enabled chip select lines (CSn), and the address lines available on unused chip
BASEADDR[23:n]
ADDRESS[n-1:0]
ADDRESS[23:n]
CS3
CS2
CS1
CS0
CS3
CS2
CS1
A16
=
CS3
CS2
A17
A16
Atmel AVR XMEGA AU
A[n-1:0]
D[7:0]
CS
A19
A18
A17
A16
Figure 27-2 on
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